Design Engineer I

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Be part of the Cadence DDR PHY IP Front End Design team responsible for -

• Developing firmware for DDR PHY using microcontrollers
• Responsible for developing firmware in C and similar Embedded programming languages typically involving bare-metal programming and developing low-level APIs on Microcontrollers.
• Responsible for collaborating with hardware designers and memory subsystem architects to derive algorithms and implement them.
• Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.
• Support debug of firmware-based simulations in hardware behavioral simulations (RTL simulations with firmware for verification)
• Support debugging issues on emulation and Silicon bring-up boards.
• Drive high-performance team culture of discipline, agility, and excellence

Required Skills:

• Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks.
• Good Knowledge of C programming language for embedded software development and use of relevant IDE.
• Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.
• Good knowledge of Shell/Perl/Python/TCL scripting
• Good debugging skills
• Good experience on Verification EDA Tools like simulators and waveform viewers

Good communication Skill

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