Digital - ASIC Design Automation Engineer

AI-Augmented Design Flows · CI/CD for RTL · Lint / CDC / Synthesis Automation

ABOUT THE ROLE

Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY technology. With Series C funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes. Here is the honest version of this job. Our digital designers spend part of every week doing work a machine should be doing: re-running lint and CDC by hand, reading thousands of violations to find the twenty that matter, chasing down which synthesis run regressed QoR, and manually assembling the evidence that a branch is clean enough to promote to release. Your job is to make that work disappear. You will own our Jenkins-based design flow infrastructure end to end and build the AI layer on top of it: agent-driven triage that filters lint and CDC noise down to the real issues, and automated pull requests that arrive pre-organized so a designer reviews a decision instead of excavating a log. The team is small enough that tooling you ship on Monday changes how it works on Tuesday. MUST BE WILLING TO WORK ONSITE - M-F

• Own the Jenkins-based CI for RTL quality across active design programs: lint, CDC, RDC, elaboration, synthesis, and STA. Optimize for turnaround time, not only coverage.
• Build the dev-to-release promotion pipeline: automated gating that qualifies a branch on clean runs and produces the handoff evidence, so promotion becomes a button rather than a checklist.
• Build synthesis and timing result tracking: per-project dashboards that make QoR regressions obvious and attributable to the commit that caused them.
• Own the front-end release methodology: release criteria, handoff checkpoints, cross-team gating, and waiver management across lint and CDC tools.
• Build agent-driven violation triage: LLM pipelines that classify lint and CDC output, suppress known-benign patterns, cluster related violations, and surface the real ones with context.
• Build automated pull requests that arrive with violations already filtered, grouped, and annotated, turning a triage session into a review.
• Implement spec-to-RTL consistency checking using LLM-driven diff and review pipelines, plus CI integrated documentation generation.
• Own evaluation and guardrails: benchmark output quality, measure false-negative rates against real violation data, and set the guardrails the team can trust.

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 3+ years building automation, CI/CD, or engineering tooling in a hardware, EDA, or infrastructure environment.
• Strong Python, plus Tcl, shell scripting, Git, Linux, and Makefiles. You are comfortable owning a codebase, not only writing scripts.
• Hands-on Jenkins (or GitLab CI / GitHub Actions) at a level where you have debugged and rearchitected a pipeline, not only used one.
• Working knowledge of the RTL front-end flow and SystemVerilog — enough to read lint and CDC output and reason about which violations matter.
• Practical experience with LLM APIs or agent frameworks (Anthropic Claude, OpenAI, or equivalent), applied to something real that other people used.
• Strong technical writing, and authorization to work in the United States or Canada as applicable to the office location; sponsorship may be considered for exceptional candidates.
• On-site Monday through Friday at our Bay Area, Vancouver, or Toronto office. This role is not remote.

• Familiarity with industry-standard EDA tools (Synopsys VCS, Verdi, PrimeTime, Design Compiler; Cadence Genus; Spyglass; Questa; JasperGold).
• Background in data engineering or ML systems: evaluation harnesses, retrieval pipelines, or production inference.
• Exposure to digital design, SoC, PHY, SerDes, or chiplet interconnect domains.
• Open-source contributions to design automation, hardware verification, or developer tooling.