ASIC Implementation Engineer, Static Verification

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.

Responsibilities

• Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC
• Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC
• Perform RTL Lint and work with the Designers to create waivers
• Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults
• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
• Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,)
• Work closely with the Design Engineers, DV Engineers, and Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Currently has a Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
• 6+ years of experience in static verification tools
• Experience with Lint, Clock Domain and Reset Domain crossing
• Experience with SOC CDC signoff
• Knowledge of SOC integration (clocking, reset, PLL, etc.)
• Knowledge of front-end ASIC flows
• Experience with RTL design using SystemVerilog or other HDL
• Experience with communicating across functional internal teams and vendors

Preferred Qualifications

• Experience with Netlist-CDC Analysis and improving MTBF
• Experience with SOC Design Integration and Front-End Implementation
• Scripting and programming experience using Perl/Python, TCL, and Make
• Experience with developing structural rule based checks for RTL & Netlist
• Experience with Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools
• Knowledge of Timing/physical libraries, SRAM Memories

US: $146,000/year to $209,000/year + bonus + equity