Sr. Staff Physical Design Engineer, EMIR Analysis & Signoff

About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations. Role Summary We are seeking a highly skilled Physical Design Engineer specializing in Power Integrity (PI) and Signoff Analysis. In this role, you will be responsible for ensuring the electrical reliability and performance of our next-generation SoCs. You will bridge the gap between physical implementation and electrical verification, focusing on static/dynamic power analysis, electromigration (EM), and IR drop mitigation to ensure robust silicon performance, leading to a successful tapeout and production silicon. Responsibilities 1. Power Analysis & Optimization Perform Static IR Drop analysis to validate the robustness of the power grid (PG) and ensure connectivity. Conduct Dynamic Voltage Drop (DVD) analysis using switching activity (VCD/FSDB) to identify hotspots during peak functional bursts. Work closely with the RTL and Architecture teams to optimize power consumption at the block and top levels. 2. Electromigration (EM) & Reliability Execute Signal EM and Power EM analysis to ensure long-term interconnect reliability. Validate current density limits across various metal layers and vias, ensuring compliance with foundry design rules (LVS/ERC). Implement fixes for EM violations through wire widening, via doubling, or rerouting. 3. Power Integrity Signoff Drive the signoff flow for deep sub-micron process nodes (e.g., 5nm, 3nm, and below). Analyze the impact of decoupling capacitor (Decap) placement on transient noise and voltage stability. Collaborate with the Physical Design team to optimize the Power Grid (PG) density versus routing congestion. 4. Methodology & Flow Development Develop and enhance automated scripts (Tcl/Python) to streamline PI analysis and reporting. Stay updated on the latest EDA tool features and foundry requirements to improve analysis accuracy and turnaround time. Working knowledge of UPF specification in Power Intent design, implementation, and verification of power gating, level shifter, and isolation. Define EM-IR signoff requirements and sign-off methodology. Define and support Static and Dynamic, thermal, electro-migration, peak current, di/dt, and effective resistance analysis Develop and support Chip-package-Co-Analysis (CPA) and Chip-Power-Model (CPM) on-die model for package & die co-design analysis Solid experiences in EM-IR sign-off with successful tape out track records Excellent hand-on experience in voltage drop analysis using Redhawk-SC Excellent hand-on experience and debugging skills of finding root cause of voltage drop and EM issues Solid background in EM-IR fundamentals, analytical aptitude and excellent attention to detail Qualifications BS/MS in Electrical Engineering 10+ years of extensive physical design experiences at both block and sub-chip level, as well as full-chip level is a plus. Deep understanding of Power Delivery Networks (PDN) and the physics of IR drop. Good knowledge of PI and EM-IR sign-off requirements. Proficiency in industry-standard PI/Signoff tools: Ansys RedHawk-SC, Cadence Voltus, or Synopsys PrimePower/Rail. Experience with Multi-Voltage (MSV) designs and UPF/CPF power intent. Knowledge of Chip Package Co-Design (CPM) and system-level power integrity. Experience in high-performance designs (AI) where dynamic power is a critical constraint. Solid experiences in timing (STA) impacts of voltage droop, and thermal effects. Programming: Strong scripting skills in Tcl, Python, or Perl for flow automation. Soft Skills: Strong analytical problem-solving abilities and the ability to work in a cross-functional environment (Front-end, PD, and Package teams). Pay Disclosure The listed base salary range for this role is $237,00 - $296,000 for San Francisco Bay Area based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs. We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com. Equal Opportunity Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law. Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at [email protected]. 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1. Power Analysis & Optimization Perform Static IR Drop analysis to validate the robustness of the power grid (PG) and ensure connectivity. Conduct Dynamic Voltage Drop (DVD) analysis using switching activity (VCD/FSDB) to identify hotspots during peak functional bursts. Work closely with the RTL and Architecture teams to optimize power consumption at the block and top levels. 2. Electromigration (EM) & Reliability Execute Signal EM and Power EM analysis to ensure long-term interconnect reliability. Validate current density limits across various metal layers and vias, ensuring compliance with foundry design rules (LVS/ERC). Implement fixes for EM violations through wire widening, via doubling, or rerouting. 3. Power Integrity Signoff Drive the signoff flow for deep sub-micron process nodes (e.g., 5nm, 3nm, and below). Analyze the impact of decoupling capacitor (Decap) placement on transient noise and voltage stability. Collaborate with the Physical Design team to optimize the Power Grid (PG) density versus routing congestion. 4. Methodology & Flow Development Develop and enhance automated scripts (Tcl/Python) to streamline PI analysis and reporting. Stay updated on the latest EDA tool features and foundry requirements to improve analysis accuracy and turnaround time. Working knowledge of UPF specification in Power Intent design, implementation, and verification of power gating, level shifter, and isolation. Define EM-IR signoff requirements and sign-off methodology. Define and support Static and Dynamic, thermal, electro-migration, peak current, di/dt, and effective resistance analysis Develop and support Chip-package-Co-Analysis (CPA) and Chip-Power-Model (CPM) on-die model for package & die co-design analysis Solid experiences in EM-IR sign-off with successful tape out track records Excellent hand-on experience in voltage drop analysis using Redhawk-SC Excellent hand-on experience and debugging skills of finding root cause of voltage drop and EM issues Solid background in EM-IR fundamentals, analytical aptitude and excellent attention to detail

BS/MS in Electrical Engineering 10+ years of extensive physical design experiences at both block and sub-chip level, as well as full-chip level is a plus. Deep understanding of Power Delivery Networks (PDN) and the physics of IR drop. Good knowledge of PI and EM-IR sign-off requirements. Proficiency in industry-standard PI/Signoff tools: Ansys RedHawk-SC, Cadence Voltus, or Synopsys PrimePower/Rail. Experience with Multi-Voltage (MSV) designs and UPF/CPF power intent. Knowledge of Chip Package Co-Design (CPM) and system-level power integrity. Experience in high-performance designs (AI) where dynamic power is a critical constraint. Solid experiences in timing (STA) impacts of voltage droop, and thermal effects. Programming: Strong scripting skills in Tcl, Python, or Perl for flow automation. Soft Skills: Strong analytical problem-solving abilities and the ability to work in a cross-functional environment (Front-end, PD, and Package teams).