Principal Design Verification Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: Join AMD’s IOHUB team and help shape the future of high-performance computing, AI, and advanced silicon design. We are looking for a Principal Design Verification Engineer who is excited to lead at the intersection of design verification, system architecture, and AI-enabled engineering. In this role, you will provide technical leadership for a high-performing front-end IP verification team, own critical verification strategy for complex HUB/Router IP, and help introduce AI-driven methods that improve quality, productivity, debug efficiency, and verification scale. This is a high-impact opportunity to influence next-generation AMD products across server, data center, client, and embedded markets while helping redefine how verification is done for the AI era. THE PERSON: We are looking for a senior technical leader who is energized by complex verification challenges and motivated by the opportunity to make a broad engineering impact. The ideal candidate combines deep DV expertise with curiosity and hands-on experience applying AI, automation, and data-driven methods to improve how engineering teams work. You are someone who: Enjoys building scalable DV methodologies that help teams deliver high-quality silicon across multiple product generations. Is excited to explore practical AI applications in verification, including debug assistance, regression triage, coverage analysis, stimulus generation, and workflow automation. Can translate emerging AI capabilities into real engineering value by piloting, measuring, and scaling tools that improve productivity and quality. Leads through technical credibility, collaboration, and clear communication across architecture, design, verification, firmware, emulation, and AI tooling teams. Mentors engineers, raises the technical bar, and helps create an environment where teams can learn, innovate, and deliver together. KEY RESPONSIBILITIES: Define and own the overall DV test plan and methodology for HUB/Router designs, ensuring scalability across product variants and future silicon generations. Partner closely with architecture, design, emulation, firmware, and subsystem verification leads to build cohesive, end-to-end verification strategies. Identify and lead practical AI/ML-assisted verification opportunities, including intelligent regression triage, failure clustering, coverage gap analysis, stimulus optimization, assertion development, debug summarization, and knowledge capture. Collaborate with AI tool developers and verification users to turn promising ideas into usable workflows, define success metrics, and guide responsible adoption in production DV environments. Use data, dashboards, regression trends, and historical failure signatures to help teams make faster, better-informed decisions during verification planning, execution, debug, and closure. Mentor DV leads and engineers across global AMD sites, including helping teams adopt AI-enabled tools effectively while maintaining engineering ownership, quality, and accountability. Anticipate architectural, methodology, and verification closure risks early, and drive systemic solutions before they impact schedule, quality, or coverage. Influence cross-functional decision-making through deep technical insight, structured tradeoff analysis, and clear collaborative communication. PREFERRED EXPERIENCE: Strong DV expertise in areas such as system architecture, PCIe protocol-layer verification, HUB/Router fabrics, coherency, virtualization, or large-scale verification infrastructure. Hands-on interest or experience applying AI-enabled tools to engineering workflows, such as regression triage, failure clustering, coverage analysis, stimulus generation, debug assistance, documentation, or productivity automation. Experience with scripting, data analysis, automation frameworks, prompt engineering, or workflow orchestration is highly valued. Strong command of modern DV methodologies, including coverage-driven verification, constrained-random verification, formal verification, emulation, debug infrastructure, and verification closure strategy. Solid understanding of computer architecture fundamentals, including pipelines, routing, ordering, caching, coherency, memory hierarchy, and load/store behavior. Excellent communication, documentation, planning, and cross-functional collaboration skills, with the ability to influence technical direction across global teams. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related discipline. #LI-MO2 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

THE ROLE: Join AMD’s IOHUB team and help shape the future of high-performance computing, AI, and advanced silicon design. We are looking for a Principal Design Verification Engineer who is excited to lead at the intersection of design verification, system architecture, and AI-enabled engineering. In this role, you will provide technical leadership for a high-performing front-end IP verification team, own critical verification strategy for complex HUB/Router IP, and help introduce AI-driven methods that improve quality, productivity, debug efficiency, and verification scale. This is a high-impact opportunity to influence next-generation AMD products across server, data center, client, and embedded markets while helping redefine how verification is done for the AI era. THE PERSON: We are looking for a senior technical leader who is energized by complex verification challenges and motivated by the opportunity to make a broad engineering impact. The ideal candidate combines deep DV expertise with curiosity and hands-on experience applying AI, automation, and data-driven methods to improve how engineering teams work. You are someone who: Enjoys building scalable DV methodologies that help teams deliver high-quality silicon across multiple product generations. Is excited to explore practical AI applications in verification, including debug assistance, regression triage, coverage analysis, stimulus generation, and workflow automation. Can translate emerging AI capabilities into real engineering value by piloting, measuring, and scaling tools that improve productivity and quality. Leads through technical credibility, collaboration, and clear communication across architecture, design, verification, firmware, emulation, and AI tooling teams. Mentors engineers, raises the technical bar, and helps create an environment where teams can learn, innovate, and deliver together. KEY RESPONSIBILITIES: Define and own the overall DV test plan and methodology for HUB/Router designs, ensuring scalability across product variants and future silicon generations. Partner closely with architecture, design, emulation, firmware, and subsystem verification leads to build cohesive, end-to-end verification strategies. Identify and lead practical AI/ML-assisted verification opportunities, including intelligent regression triage, failure clustering, coverage gap analysis, stimulus optimization, assertion development, debug summarization, and knowledge capture. Collaborate with AI tool developers and verification users to turn promising ideas into usable workflows, define success metrics, and guide responsible adoption in production DV environments. Use data, dashboards, regression trends, and historical failure signatures to help teams make faster, better-informed decisions during verification planning, execution, debug, and closure. Mentor DV leads and engineers across global AMD sites, including helping teams adopt AI-enabled tools effectively while maintaining engineering ownership, quality, and accountability. Anticipate architectural, methodology, and verification closure risks early, and drive systemic solutions before they impact schedule, quality, or coverage. Influence cross-functional decision-making through deep technical insight, structured tradeoff analysis, and clear collaborative communication. PREFERRED EXPERIENCE: Strong DV expertise in areas such as system architecture, PCIe protocol-layer verification, HUB/Router fabrics, coherency, virtualization, or large-scale verification infrastructure. Hands-on interest or experience applying AI-enabled tools to engineering workflows, such as regression triage, failure clustering, coverage analysis, stimulus generation, debug assistance, documentation, or productivity automation. Experience with scripting, data analysis, automation frameworks, prompt engineering, or workflow orchestration is highly valued. Strong command of modern DV methodologies, including coverage-driven verification, constrained-random verification, formal verification, emulation, debug infrastructure, and verification closure strategy. Solid understanding of computer architecture fundamentals, including pipelines, routing, ordering, caching, coherency, memory hierarchy, and load/store behavior. Excellent communication, documentation, planning, and cross-functional collaboration skills, with the ability to influence technical direction across global teams. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related discipline. #LI-MO2 #LI-Hybrid

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.