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Open nowPosted 7 days ago

Senior Debug Verification Engineer

Altera56 open roles

Where
San Jose, California, United States
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Your applicationOpen nowSenior Debug Verification EngineerAltera · San Jose, California, United States

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The clock on this job

Early applications get read.

8.0% of postings close within 7 days. Measured by our own scanner across the market. Altera postings stay open a median of 3 days.

Share of postings closed within
  1. 1.6%1 day
  2. 3.6%3 days
  3. 8.0%7 days
  4. 15.0%14 days
  5. 34.2%30 days
This job: posted 7 days ago

Altera median: 3 days open

The posting

Job Details:

Job Description:

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

As a Sr. Debug Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.

Key Responsibilities:

  • Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
  • Create testcase and testbench with UVM methodology
  • Fullchip/system functional verification, by defining verification strategies/methodology​​ and test plan to enable effective verification
  • Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.
  • Experience with ARM and RISC Debug Architectures is desired with focus on design verification.
  • Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.
  • Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
  • Experience on Emulation will be an add on.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149,100 - $215,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

#MD-1

Qualifications:

Minimum Qualifications

  • 8+ years of experience with complex ASIC designs and/or verification
  • 8+ years of experience with SystemVerilog language
  • 8+ years of experience on UVM verification methodology, and formal verification method
  • 8+ years of experience scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.
  • Strong communication skills and the ability to work with a team spread across different geography sites

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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