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Open nowPosted 2 days ago

ASIC Design Engineer – Fabric/Interconnect

Apple5,832 open roles

Where
Austin, United States of America
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Your applicationOpen nowASIC Design Engineer – Fabric/InterconnectApple · Austin, United States of America

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The clock on this job

Early applications get read.

9.0% of postings close within 7 days. Measured by our own scanner across the market. Apple postings stay open a median of 31 days.

Share of postings closed within
  1. 1.8%1 day
  2. 3.9%3 days
  3. 9.0%7 days
  4. 15.5%14 days
  5. 33.9%30 days
This job: posted 2 days ago

Apple median: 31 days open

The posting

Summary

At Apple, phenomenal ideas have a way of becoming great products and customer experiences very quickly. The industry is accustomed to Apple taping out the SOC’s for our various products at a rigorous pace. In order to achieve this, Apple’s best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high transparency and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design. Our position requires knowledge of interconnect fabrics and system memory hierarchy

Description

-Design & Integration of coherent and non-coherent fabrics into a subsystem or SoC with good understanding of on-chip interconnect architectures (NoC topologies, crossbars, arbitration). - Own all aspects of RTL development design, templating, scripting and RTL generation. - Work and collaborate with other designers in the group to deliver results. - Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block. - Work with front-end synthesis/STA teams to ensure timing for the block is met. - Work with power/performance and functional verification team to ensure high quality of the block. - Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process

Minimum Qualifications

Minimum of BS + 0 years relevant industry experience.

Preferred Qualifications

Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy. A consistent track record of delivering large, sophisticated designs in high volume production for low power applications Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on time Strong interpersonal skills, as the candidate will work with diverse groups within the company Self-starter, highly motivated, highly organized, and schedule driven Familiarity with all front-end tools including lint, CDC, synthesis

EEO Statement

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

Accessibility

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Learn about reasonable accommodations for job applicants

Application Deadline

Apple accepts applications to this posting on an ongoing basis.

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