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STA Engineer

Apple6,577 open roles

Where
Beaverton, United States of America
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Your applicationOpen nowSTA EngineerApple · Beaverton, United States of America
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The clock on this job

Early applications get read.

13.5% of postings close within 7 days. Measured by our own scanner across the market. Apple postings stay open a median of 41 days.

Share of postings closed within
  1. 2.3%1 day
  2. 4.6%3 days
  3. 13.5%7 days
  4. 21.8%14 days
  5. 36.6%30 days
  6. 58.9%60 days
This job: posted today

Apple median: 41 days open

The posting

Summary

Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers.

Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables.

Description

As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.

Minimum Qualifications

Bachelors Degree + 10 Years of Experience

Preferred Qualifications

Strong fundamentals in the area of Digital design Self-starter and highly motivated Proficient in scripting languages (TCL and Perl) Familiarity with ASIC design timing concepts Exposure in STA tools (Primetime) is a plus Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks Familiarity in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable but not required Knowledge of timing corners/modes, process variations and signal integrity related issues is a plus Ability to commnicate optimally across all internal groups

EEO Statement

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

Accessibility

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Learn about reasonable accommodations for job applicants

Application Deadline

Apple accepts applications to this posting on an ongoing basis.

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