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Test Development Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED

Pay
SGD 6,000 – SGD 12,000 a month
Where
North, Singapore
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Your applicationOpen nowTest Development EngineerAVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED · North, Singapore

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Share of postings closed within
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  2. 4.5%3 days
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  4. 19.7%14 days
  5. 35.6%30 days
  6. 58.0%60 days
This job: posted today

The posting

Role Summary

We are looking for a dedicated Test Development Engineer to lead the definition, architecture, and execution of test solutions for our NPI silicon programs. You will be the technical authority responsible for the "First Silicon" bridge—translating complex design specifications into robust, production-ready ATE test programs. This role is critical in accelerating time-to-market by ensuring that characterization, verification, and manufacturing test coverage are unified early in the design cycle.

Core Responsibilities

  • Test Program Architecture & Strategy: Lead the development of comprehensive test strategies from pre-silicon to mass production. Define test flow architecture, including wafer sort, final test, and system-level test (SLT) requirements to ensure high-quality delivery.
  • "First Silicon" Bring-up: Drive the hands-on bring-up of first-pass silicon. Own the debug loop between ATE platforms and silicon, resolving critical path issues such as power delivery, signal integrity, and firmware-hardware interaction.
  • Test Development & Programming: Develop, implement, and validate complex ATE test programs (Advantest V93000/ExaScale) for next-generation chips. Utilize C++/Python/Java to automate test pattern generation, characterization scripts, and data analysis pipelines.
  • Test Hardware Integration: Collaborate with PCB and probe card designers to optimize test hardware for power and signal integrity at high speed (PCIe Gen6, HBM4, Maxphy, 400G+ SerDes). Actively debug hardware-software interface issues on the loadboard and probe card levels.
  • Design-for-Test (DFT) Influence: Partner with design teams to ensure DFT features (Scan, MBIST, Boundary Scan and various IP) are effectively integrated and utilized in the test flow. Provide feedback on design hooks to improve testability and reduce test time (TTR).
  • Characterization & Optimization: Perform rigorous PVT (Process, Voltage, Temperature) characterization experiments to establish product guard-bands. Drive initiatives to optimize test time and test coverage before the product reaches volume manufacturing.
  • Cross-Functional Technical Lead: Serve as the primary technical point of contact for IP owners, DFT engineers, and assembly/test partners. Communicate debug findings, yield limiters, and hardware limitations clearly to drive design corrections.

Technical Qualifications

  • Platform Expertise: Proven experience developing ATE test programs on Advantest SmartScale (PS1600) or ExaScale (PS5000) platforms.
  • Language Proficiency: Advanced programming skills in C++, Python, and Perl, with the ability to write robust, maintainable test code.
  • Silicon Fundamentals: Deep understanding of silicon physics, ESD, latch-up, and the challenges of testing at advanced nodes (1.4nm/2nm/3nm).
  • Hardware Knowledge: Strong grasp of high-speed electronics, transmission line theory, power delivery and test hardware design (loadboards, sockets, and thermal control).
  • NPI Lifecycle: Demonstrated success in navigating the NPI milestones—from tape-out to qualification and high-volume transfer.

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