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Sr ASIC Design Engineer

Blue Origin1,857 open roles

Where
Kraków, Poland
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Your applicationOpen nowSr ASIC Design EngineerBlue Origin · Kraków, Poland
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The clock on this job

Early applications get read.

13.3% of postings close within 7 days. Measured by our own scanner across the market. Blue Origin postings stay open a median of 17 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.6%3 days
  3. 13.3%7 days
  4. 21.3%14 days
  5. 35.7%30 days
  6. 59.1%60 days
This job: posted today

Blue Origin median: 17 days open

The posting

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

Blue Origin is pioneering the future of space-based connectivity with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This network will service tens of thousands of enterprise, data center, and government users who require reliable connectivity for critical operations.

This is a foundational role within our Silicon Systems Development team. To further Blue Origin's mission of millions of people living and working in space for the benefit of Earth, we are bringing together technology from across our product lines to build the future of space-based communication.

Key Responsibilities:

  • Design and develop FPGAs, digital ASICs, and/or mixed-signal ASICs
  • Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog)
  • Develop verification methodologies and test benches for block and system-level verification
  • Create and execute test plans, develop test harnesses, and implement coverage models
  • Conduct timing analysis, noise analysis, and other signoff checks
  • Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering
  • Support lab integration and troubleshooting activities
  • Resolve design issues and drive solutions for timing, congestion, and other implementation challenges

Basic Qualifications:

  • 7+ years of experience in ASIC design and implementation
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
  • Experience with FPGA & ASIC design
  • Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)
  • Experience with Linux development environment
  • Experience with design verification and test bench development

Preferred Skills and Experience:

  • Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
  • Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)
  • Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPs
  • Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM)
  • Strong object-oriented programming and scripting skills (Python, TCL, Perl)
  • Experience with physical design flows and industry-standard EDA tools
  • Experience with RTL2GDSII physical design and signoff flows
  • Knowledge of deep sub-micron FinFET and CMOS technologies
  • Experience with DFT/Scan/MBIST/LBIST methodologies
  • Experience mentoring junior engineers

Culture Statement

Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.

Candidates may be subject to verification and BGS screening as per applicable law.

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