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Open nowPosted 8 days ago

ASIC Design Verification Engineer

Broadcom351 open roles

Where
USA CA Irvine Alton Parkway Bldg 2
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Your applicationOpen nowASIC Design Verification EngineerBroadcom · USA CA Irvine Alton Parkway Bldg 2

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  2. CV RocketCV written for this posting.

  3. 25 readersRecruiter, hiring manager, skeptic. Round after round.

  4. CV RocketApplied on Broadcom's own form.

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The clock on this job

Early applications get read.

11.9% of postings close within 7 days. Measured by our own scanner across the market. Broadcom postings stay open a median of 43 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.4%3 days
  3. 11.9%7 days
  4. 18.6%14 days
  5. 35.6%30 days
  6. 45.1%60 days
This job: posted 8 days ago

Broadcom median: 43 days open

The posting

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Job Description:

Would you like to become part of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating devices that accelerate AI/ML workflows! This team develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency.

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an extremely skilled and efficient group of engineers.

This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for technical leadership.

Skills: Self motivated personality with a strong presence to do things right. Need to have a strong sense of teamwork and ability to work well with other. Constrained random verification methodologies with experience driving completion via coverage closure.

Preferable to have skills with SV and UVM, well versed in OOP

Tools/Languages: System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...)

Experience: Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience

Compensation and Benefits

The annual base salary range for this position is To

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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