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Principal Product Validation Engineer

Cadence Design Systems684 open roles

Where
NOIDA
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Your applicationOpen nowPrincipal Product Validation EngineerCadence Design Systems · NOIDA

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The clock on this job

Early applications get read.

13.9% of postings close within 7 days. Measured by our own scanner across the market. Cadence Design Systems postings stay open a median of 56 days.

Share of postings closed within
  1. 2.2%1 day
  2. 4.7%3 days
  3. 13.9%7 days
  4. 22.4%14 days
  5. 38.1%30 days
  6. 59.0%60 days
This job: posted today

Cadence Design Systems median: 56 days open

The posting

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role Summary

Lead an experienced Product Verification team responsible for quality across multiple Verisium product lines and leading-edge technologies in development. This role combines deep design verification expertise, proven people leadership, cross-functional execution, and a passion for advancing AI-assisted verification and debug.

Key Accountabilities

  • People leadership: Lead and develop an experienced PV team with clear direction, ownership, and quality standards.
  • Product quality: Own verification strategy and release readiness across multiple Verisium product lines.
  • Technical leadership: Guide test strategy, coverage, regressions, failure triage, and root-cause analysis.
  • Cross-functional execution: Align R&D, product, field, and customer teams on priorities and quality risks.
  • Operational excellence: Improve verification efficiency, predictability, and automation.
  • Innovation: Advance AI-assisted verification and debug through intelligent triage, root-cause analysis, and workflow automation.
  • Customer impact: Help resolve critical customer issues and strengthen product adoption.

Candidate Profile

  • Experience: Around 10 years in design verification, with experience delivering complex programs across multiple products and emerging technologies.
  • Technical depth: Strong expertise in verification methodologies, testbench architecture, coverage, debug, regressions, SystemVerilog, and UVM; exposure to simulation, formal, emulation, or hardware-assisted verification.
  • Leadership: Proven success leading and developing experienced engineering teams.
  • Collaboration: Ability to work effectively across R&D, product, field, support, and customer-facing teams.
  • Innovation: Passion for AI-assisted verification and debug; experience with Python, automation, or data-driven engineering is valuable.
  • Industry knowledge: Understanding of semiconductor verification workflows and EDA products.
  • Communication: Strong technical judgment, execution discipline, and communication skills.
  • Education: Bachelor’s or master’s degree in electrical engineering, computer engineering, computer science, or equivalent experience.

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