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Open nowPosted yesterday

Lead Analog Layout Engineer

Ciena166 open roles

Pay
CA$141,700 – CA$226,000 a year
Where
Remote Canada
Work mode
Remote
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Your applicationOpen nowLead Analog Layout EngineerCiena · Remote Canada

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The clock on this job

Early applications get read.

13.8% of postings close within 7 days. Measured by our own scanner across the market. Ciena postings stay open a median of 21 days.

Share of postings closed within
  1. 2.2%1 day
  2. 4.7%3 days
  3. 13.8%7 days
  4. 22.3%14 days
  5. 37.8%30 days
  6. 59.0%60 days
This job: posted yesterday

Ciena median: 21 days open

The posting

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.

The Lead Analog Layout Engineer shapes the high-speed silicon behind Ciena's WaveLogic coherent optical communications products by owning critical analog and mixed-signal layouts from feasibility through tapeout. This hands-on individual-contributor technical leadership role sets layout direction, coordinates delivery with circuit designers and layout contributors, and advances implementation in advanced CMOS technologies. The role builds on more than 30 years of team innovation in high-speed ADC and DAC macros for coherent optical transmission while extending capabilities into high-speed SerDes.

How you will make an impact:

  • Own assigned layout projects from feasibility and floorplanning through implementation, physical verification, integration, and tapeout readiness.
  • Define project scope, implementation plans, effort estimates, milestones, and review checkpoints with circuit designers and engineering leads; coordinate contributors, track dependencies, and resolve implementation bottlenecks.
  • Lead layout reviews and quality checks with the layout team and circuit designers.
  • Partner with circuit designers to establish implementation constraints and evaluate performance, area, device matching, parasitics, isolation, and reliability tradeoffs.
  • Develop layout strategies for performance-critical circuits and high-speed signal paths; review extracted parasitics and implement targeted improvements.
  • Drive physical-verification and reliability closure, including DRC, LVS, ERC, antenna, BUMP, EM/IR, and PERC checks.
  • Mentor junior engineers through hands-on problem-solving and design feedback; partner with CAD and AI/ML engineers on environment setup, tool evaluation, automation, reusable layout structures, RFIC and analog layout generation, PCell development, and design space exploration; communicate progress, risks, and corrective actions against milestones.

The must haves:

  • Education: Bachelor's degree or higher in Electrical Engineering, or a related field.
  • Experience: 5+ years of custom analog or mixed-signal IC layout experience, including ownership of complex layouts through successful tapeouts, independent technical decision-making, project delivery, guidance of layout contributors, and hands-on implementation.
  • Application of layout expertise in one or more circuit families, such as ADCs, DACs, SerDes, PLLs, high-speed amplifiers, or precision analog circuits.
  • Utilization of Cadence Virtuoso and Siemens Calibre, or comparable custom-layout and physical-verification tools.
  • Application of device matching, parasitic resistance and capacitance, coupling, high-frequency routing, shielding, ESD-aware layout, electromigration, and IR drop.
  • Application of deep-submicron CMOS processes, foundry design rules, device isolation, and layout-dependent effects to performance and reliability challenges.
  • Collaboration with circuit designers, analytical problem-solving, attention to layout quality, and communication of technical tradeoffs.

Nice to haves:

  • Practical experience with FinFET layout and advanced-node implementation.
  • Experience in high-speed SerDes or data converters.
  • Ansys Totem or comparable EM/IR tools and PERC-based ESD and reliability debugging.
  • Deep knowledge of noise isolation and shielding.
  • PCell development and layout automation skills.
  • Experience using AI-assisted coding tools to develop and validate layout-flow scripts, automation, and engineering utilities.

Pay Range:

The annual pay range for this position in Canada is C$141,700 - C$226,000.

#LI-BS1

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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