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Open nowFirst seen 81 days ago

ASIC Physical Design Engineer

Cisco1,237 open roles

Where
Caesarea, Israel
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Your applicationOpen nowASIC Physical Design EngineerCisco · Caesarea, Israel

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The clock on this job

Early applications get read.

13.3% of postings close within 7 days. Measured by our own scanner across the market. Cisco postings stay open a median of 25 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.6%3 days
  3. 13.3%7 days
  4. 21.3%14 days
  5. 35.7%30 days
  6. 59.1%60 days
This job: first seen 81 days ago

Cisco median: 25 days open

The posting

Cisco Silicon One is seeking a Physical Design Engineer.

Meet the Team

The Physical Design team within Cisco Silicon One owns backend methodology and flow development from RTL to GDS. The team plays a critical role in developing high-quality VLSI designs for some of Cisco's most advanced silicon products.

We work with the latest silicon technologies and processes to build large-scale, complex devices that push the boundaries of feasibility. You will collaborate with experienced engineers across architecture, design, verification, and implementation to deliver high-performance silicon.

Your Impact

You will be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. As a Physical Design Engineer, you will contribute to backend implementation work across key stages of chip design, helping move complex designs from RTL toward GDS.

You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.

  • Contribute to physical synthesis, place and route, optimization, and timing closure for complex VLSI designs.
  • Support design floor planning and implementation planning in collaboration with senior physical design engineers.
  • Analyze timing, congestion, power, area, and design-rule issues and help drive them toward closure.
  • Work with physical design verification flows, including LVS and DRC, to support clean implementation handoff.
  • Partner with cross-functional teams to debug implementation issues and improve backend flow quality.

Minimum Qualifications:

  • B.Sc. or M.Sc. in Electrical Engineering or a related field.
  • 2+ years of hands-on experience in VLSI backend design or a relevant physical design domain.
  • Strong understanding of the Place & Route flow.
  • Hands-on experience with physical synthesis, place and route, optimization, timing closure, or design floor planning.

Preferred Qualifications:

  • Understanding of physical construction and integration concepts across backend implementation.
  • Knowledge of physical design verification methodology, including LVS and DRC.
  • Familiarity with physical design EDA tools such as Synopsys, Cadence, or similar platforms.
  • Ability to learn independently, take ownership of assigned tasks, and work effectively with teammates.
  • Strong problem-solving skills and attention to detail in complex technical environments.

#li-as6

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

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