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Open nowPosted 504 days ago

RTL Design

Codersbrain

Where
Bangalore , hyderabad
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Your applicationOpen nowRTL DesignCodersbrain · Bangalore , hyderabad

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Share of postings closed within
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  2. 4.3%3 days
  3. 11.5%7 days
  4. 18.1%14 days
  5. 35.6%30 days
  6. 44.6%60 days
This job: posted 504 days ago

The posting

RTL Design

## Company Overview Information about the company, its industry, and culture is not provided.

## Job Summary The RTL Design role involves designing and implementing complex microarchitectures and intellectual property (IP) in Register Transfer Level (RTL). The successful candidate will contribute to the design and verification processes, ensuring adherence to design specifications and quality standards.

## Responsibilities - Build microarchitectures for various digital designs and components. - Implement IP in RTL using industry-standard methodologies and tools. - Perform CDC (Clock Domain Crossing) and Lint analysis to ensure design reliability and correctness. - Utilize scripting languages such as TCL, Perl, and Python for automation and tool integration. - Generate synthesis constraints to facilitate the synthesis process and ensure optimal performance. - Collaborate with cross-functional teams to validate design and address any issues that arise during implementation.

## Qualifications - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - 4 to 8 years of experience in RTL design and verification. - Strong knowledge of microarchitecture principles and RTL coding practices. - Hands-on experience in UPF (Unified Power Format) for low power design. - Proficiency in CDC and Lint analysis tools. - Familiarity with scripting languages: TCL, Perl, and Python. - Experience in generating synthesis constraints for various RTL designs.

## Preferred Skills - Experience with design verification methodologies such as UVM (Universal Verification Methodology). - Knowledge of hardware description languages (HDLs) such as Verilog or VHDL. - Familiarity with FPGA and ASIC design flows.

## Experience Candidates must have a minimum of 4 years of relevant experience in RTL design.

## Environment The positions are available in Bangalore and Hyderabad, and are offered as full-time roles. The work setting is primarily office-based.

## Salary Salary details are not specified.

## Growth Opportunities Information regarding career advancement opportunities within the company is not provided.

## Benefits Details about offered benefits are not specified.

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