Skip to content
CV Rocket
Get started
How it worksThe enginePricingBlogContactSign in

Open nowPosted 246 days ago

Lead Digital Verification Engineer

Efficient Computer25 open roles

Pay
$200,000 – $260,000 a year
Where
San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Get the CV for this job

From $25 per CV, paid once. No subscription.

Your applicationOpen nowLead Digital Verification EngineerEfficient Computer · San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX

  1. YouYes, apply to this one.

  2. CV RocketCV written for this posting.

  3. 25 readersRecruiter, hiring manager, skeptic. Round after round.

  4. CV RocketApplied on Efficient Computer's own form.

The reply lands in your private mailbox

3×more interviews than doing it yourself with ChatGPT.

The clock on this job

Early applications get read.

11.8% of postings close within 7 days. Measured by our own scanner across the market. Efficient Computer postings stay open a median of 43 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.4%3 days
  3. 11.8%7 days
  4. 18.6%14 days
  5. 35.6%30 days
  6. 45.1%60 days
This job: posted 246 days ago

Efficient Computer median: 43 days open

The posting

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.

We are looking for an experienced Design Verification Lead to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedule The DV Lead will help shape our internal processes for building robust and verified designs, including the company’s second product line, which will scale computing performance and capability, while improving energy efficiency.

This is a unique opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

  • Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones
  • Author and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteria
  • Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors
  • Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases
  • Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning
  • Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs
  • Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions
  • Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams
  • Debug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases
  • Own the bug lifecycle — triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects
  • Manage the regression framework — defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines
  • Coordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environments
  • Collaborate cross-functionally with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teams
  • Lead, mentor, and grow the verification engineering team while maintaining a high quality bar through rigorous reviews
  • Represent verification readiness in tapeout sign-off reviews and program-level decisions
  • Support running gate-level simulations as part of design signoff.
  • Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.

Required Qualifications & Experience

  • Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience: 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution.
  • UVM Mastery: Deep expertise in UVM-based testbench architecture and constrained-random verification methodology — not just usage, but architectural decision-making and optimization.
  • SystemVerilog: Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages.
  • Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
  • Debug Skills: Proven ability to debug deeply complex simulation failures spanning multiple design blocks, protocols, and abstraction levels.
  • SoC Architecture: Strong understanding of modern SoC building blocks — processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
  • Scripting & Automation: Proficiency in Python, Perl, or Tcl for test automation, log analysis, coverage post-processing, and regression flow development.
  • Communication: Clear and effective communication of verification status, risk, and trade-offs to technical peers and program leadership.

We offer a competitive base salary for this role, generally ranging from $200,000 to $260,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.

Why Join Efficient?

Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.

From $25, paid onceGet the CV for this job

What happens when you press

One press. We do the rest.

  1. A CV for this posting

    Written against Efficient Computer's own wording, from every piece of relevant proof in your profile.

  2. 25 readers review it

    Recruiter, hiring manager, skeptic and more read every draft, round after round. You get the best round.

    The review screen in CV Rocket: how each CV was read, round by round.

  3. We apply on Efficient Computer's form

    Our application engine gets through the hardest forms there are. Where a question needs you, AI suggests the best answer. Don't want us applying from our IP addresses? Use our Chrome extension: we apply straight from your own browser.

    An application in CV Rocket: every answer filled in on the employer's form.

  4. Every reply, sorted

    Efficient Computer's answer lands in your private mailbox, and we classify it on arrival: interview, question, rejection.

    The CV Rocket inbox: each employer reply classified as an interview, an action or a rejection.

  5. Reply with AI

    AI helps you write the email, checks it and sends it. We show you whether the recruiter read it.

  6. The interview in your calendar

    Full integration with your calendar. The invitation goes straight in.

    An interview invitation in the CV Rocket inbox, added to the candidate's calendar.
Get the CV for this job

From $25 per CV, paid once. No subscription.

Why it works

3×

more interviews than doing it yourself with ChatGPT.

ChatGPT writes a CV and never learns what happened to it. We see every reply. For each CV we know:

  • How it was written, and how the review scored it
  • When we applied, and how long after the posting went up
  • Which posting, which company, which city
  • Who got the interview, and who heard nothing

That is how we know which CVs get called.

Get the CV for this job

From $25 per CV, paid once. No subscription.

The numbers game

More applications. More interviews.

Every application goes out with its own CV, written for that posting and paid once. Send enough of them and the law of large numbers finds you the job.

Get the CV for this job
By hand5–10
With CV Rocket100
applications a day

Nearby

Live postings like this one

Same employer first, then the same role elsewhere.

Before you press

Straight answers

Get the CV for this job

From $25 per CV, paid once. No subscription.

What if my background isn't good enough?

We make the most of the background you have. The CV uses every piece of relevant proof your profile holds, and one of the 25 readers reads your whole profile and flags what the CV left out.

Do you really apply for me?

Yes, on the employer's own form, the hardest ones included. Where a question needs you, you answer it right there and AI suggests the best answer. Don't want us applying from our IP addresses? Use our Chrome extension: we apply straight from your own browser.

Is it a subscription?

No. You pay once per CV, from $25. Every application goes out with its own CV, written for that posting.

One job. One CV.
Paid once.

Pick the posting you want. We write for it, apply for you and catch the reply.

Get the CV for this job

From $25 per CV, paid once. No subscription.