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Sr Principal SoC DFT Engineer

GlobalFoundries849 open roles

Where
IND - Karnataka - Bengaluru - Central
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Your applicationOpen nowSr Principal SoC DFT EngineerGlobalFoundries · IND - Karnataka - Bengaluru - Central
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The clock on this job

Early applications get read.

13.7% of postings close within 7 days. Measured by our own scanner across the market. GlobalFoundries postings stay open a median of 17 days.

Share of postings closed within
  1. 2.3%1 day
  2. 4.8%3 days
  3. 13.7%7 days
  4. 22.1%14 days
  5. 37.6%30 days
  6. 59.1%60 days
This job: posted yesterday

GlobalFoundries median: 17 days open

The posting

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com

Introduction

GlobalFoundries is seeking a Senior Principal SoC Design-for-Test Engineer to serve as a senior technical authority for complex custom SoC designs. The successful candidate will define DFT strategy and architecture, solve critical problems of exceptional complexity, drive scalable innovation across programs, and influence cross-functional technical direction from concept through high-volume manufacturing.

Key Responsibilities:

  • Define DFT strategy, architecture, methodology, and signoff criteria for complex SoCs and multiple interdependent technical areas.
  • Lead high-impact DFT initiatives spanning planning, risk management, execution, manufacturing readiness, silicon quality, and test cost.
  • Architect scalable solutions for scan and ATPG, compression, memory test and repair, logic BIST, test access, boundary scan, IJTAG, and mixed-signal test.
  • Establish readiness and signoff frameworks, close critical risks, and provide evidence-based recommendations to engineering and program leadership.
  • Solve critical DFT problems of exceptional complexity and establish reusable approaches across products and teams.
  • Lead cross-functional resolution of issues involving architecture, RTL, DV, PD, firmware, product engineering, manufacturing test, and post-silicon teams.
  • Drive DFT innovation, automation, and technical tradeoffs while mentoring senior engineers and influencing customers, partners, and senior stakeholders.

Other Responsibilities

  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs

Required Qualifications

  • Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 10+ years of relevant experience; or bachelor’s degree with 15+ years of relevant experience.
  • Exceptional mastery of SoC DFT and demonstrated recognition as a senior technical authority across programs or technical areas.
  • Expert-level experience with scan and ATPG, compression, memory test and repair, test clocking and access, boundary scan, and hierarchical DFT.
  • Experience defining DFT implementation, verification, readiness, and signoff criteria across IP, subsystem, partition, and SoC levels.
  • Experience across the silicon lifecycle, including architecture, RTL integration, physical implementation, pattern generation, tapeout, silicon bring-up, and high-volume manufacturing.
  • Deep understanding of fault models, test coverage, diagnosis, outgoing quality, test time, manufacturing risk, and test cost.
  • Experience with major DFT EDA toolchains (prefer SNPS) and automation using Python, Tcl, Perl, Shell, or equivalent languages.
  • Demonstrated ability to solve exceptionally complex problems, lead across organizational boundaries, influence senior stakeholders, and communicate technical and business tradeoffs.

Preferred Qualifications

  • Experience with advanced DFT methodologies such as hierarchical ATPG, streaming scan, logic BIST, scan diagnosis, cell-aware test, or lifecycle test.
  • Experience with memory repair, NVM test, eFuse, IEEE 1149.1 boundary scan, IEEE 1687 IJTAG.
  • Experience with low-power, tester-correlation, silicon-debug, and high-reliability DFT requirements.
  • Track record of developing reusable DFT architectures, automation, reference flows, and signoff methodologies across multiple SoC programs.

GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

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