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Senior Full-Custom Silicon Analog Design Engineer, Raxium

Google3,388 open roles

Where
Fremont, CA, USA
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Your applicationOpen nowSenior Full-Custom Silicon Analog Design Engineer, RaxiumGoogle · Fremont, CA, USA

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The clock on this job

Early applications get read.

12.3% of postings close within 7 days. Measured by our own scanner across the market. Google postings stay open a median of 29 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.5%3 days
  3. 12.3%7 days
  4. 19.3%14 days
  5. 35.6%30 days
  6. 58.1%60 days
This job: first seen 1 hour ago

Google median: 29 days open

The posting

In most instances, this position requires in-person interviews as part of the hiring process

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
  • 8 years of full-custom SOC design experience.
  • Experience supporting tape-outs of analog and mixed-signal circuits in advanced CMOS nodes (e.g., 22nm, 12nm, FinFET).
  • Experience with standard electronic design automation (EDA) layout, parasitic extraction, and schematic simulation tools (e.g., Virtuoso, Spectre, Calibre, Primsim, or HSPICE).
  • Experience with transistor-level design of full-custom analog modules.

Preferred qualifications:

  • Master’s degree or PhD in Electrical Engineering or related field.
  • Experience in full-custom Pixel Array IP creation, MicroLED or display backplanes, and active-matrix architectures.
  • Experience in Silicon Memory Implementation like Static Random Access Memory (SRAM) cell design or low-power memory structures.
  • Experience in ultra-low-power management systems, including regulators and charge pumps.
  • Experience with patented technology or publications in conferences or journals.
  • Experience using AI for analog design.

About the job

We are seeking a highly skilled and experienced Senior Full-Custom Silicon Analog Design Engineer with customer-owned tooling (COT) and complementary metal-oxide semiconductor (CMOS) expertise to join our dynamic team and develop the next generation of our cutting-edge silicon for MicroLED-based microdisplay CMOS backplane.

In this role, you will be responsible for the design, simulation, and guide the layout of high-performance analog and mixed-signal circuits in advanced CMOS technologies. You will play a key role in the development of next-generation products, contributing to all phases of the analog custom design from concept to production.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

  • Lead end-to-end full-custom analog modules, encompassing analog IP specifications, architectural definition, seamless integration, and extensive transistor-level design and simulation.
  • Participate in full-chip integration and full-custom Pixel Array IP creation, architecting specialized MicroLED drivers for individual pixel diodes and meeting constraints.
  • Drive transistor-level innovations for ultra-low-power and low-voltage operation across custom logic, standard cells, and ultra-low-power Static Random-Access Memory (SRAM) memory blocks, reducing active and standby power dissipation.
  • Direct physical layout guidance and parasitic optimization. Partner closely with layout designers on critical floorplanning, symmetry, shielding, matching, and electromigration/IR-drop sign-off.
  • Collaborate closely with RTL designers, micro-architecture teams, and mixed-mode simulation groups using advanced modeling (Verilog-AMS, SystemVerilog RNM) to optimize chip performance, while co-leading post-tapeout silicon bench characterization and debug.
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