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Open nowFirst seen 4 hours ago

SoC Limits Management Lead

Google3,315 open roles

Where
Mountain View, CA, USA; San Diego, CA, USA
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Your applicationOpen nowSoC Limits Management LeadGoogle · Mountain View, CA, USA; San Diego, CA, USA

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The clock on this job

Early applications get read.

8.1% of postings close within 7 days. Measured by our own scanner across the market. Google postings stay open a median of 26 days.

Share of postings closed within
  1. 1.7%1 day
  2. 3.6%3 days
  3. 8.1%7 days
  4. 15.1%14 days
  5. 34.0%30 days
This job: first seen 4 hours ago

Google median: 26 days open

The posting

In most instances, this position requires in-person interviews as part of the hiring process. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
  • 15 years of industry experience in Power Management or Low-Power Design/Methodology.
  • Experience navigating the full product delivery cycle, from initial architecture definition through to post-silicon productization.
  • Experience with low-power architectures and advanced power optimization techniques.

Preferred qualifications:

  • MS or PhD in Electronics or Computer Engineering, or equivalent, with a focus on computer architecture and power/performance analysis.
  • Experience in peak power management, in-rush current, PDN droop detection and mitigation, adaptive clock distribution, aging and process monitors, power aware floorplanning, battery technology, concurrency management and thermal management.
  • Exceptional leadership and influencing skills, with an ability to influence cross-functional roadmaps and drive ROI-based technical decisions.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a SoC Limits Management Lead in the System Power and Performance team, you will be responsible for defining how our next-generation systems balance high performance against physical and electrical constraints. You will bridge the gap between hardware IP, system software, and product requirements to design a holistic "Limits Management" subsystem. Your work ensures our SoCs deliver maximum performance under peak current constraints, while maintaining long-term reliability and stability.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

  • Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
  • Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.
  • Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
  • Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies.
  • Drive organizational consensus on feature return on investment (ROI) and oversee Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.
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