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Open nowPosted today

Logic Design Engineer

IBM2,312 open roles

Where
Bangalore, IN
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Your applicationOpen nowLogic Design EngineerIBM · Bangalore, IN

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The clock on this job

Early applications get read.

8.2% of postings close within 7 days. Measured by our own scanner across the market. IBM postings stay open a median of 6 days.

Share of postings closed within
  1. 1.8%1 day
  2. 3.6%3 days
  3. 8.2%7 days
  4. 15.2%14 days
  5. 34.0%30 days
This job: posted today

IBM median: 6 days open

The posting

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

  • Collaborate with micro architect, designers to implement CPU micro architectural features to solve PPA problems on targeted workloads.
  • Collaborate with Silicon Bringup team and Software team to verify and debug microarchitecture and its performance.
  • Strong ability to communicate and drive to closure micro architectural proposals within Core and Cache team with technical stakeholders across Chip/System with presentation and documents.
  • Strong collaborative and interpersonal skills and a proven ability to guide new design team members
  • 5-10 years experience in high performance microprocessor architecture, micro architecture, computer architecture.
  • Deep knowledge of Processor Instruction set architecture (e.g ARM, X86, Power).
  • Deep understanding/experience of CPU microarchitecture and architecture with experience in: Fetch, Decode, Load-Store, L1, L2 caches, Prefetch, Coherency
  • Memory Design, Memory Ordering Rules, Load- Store, Pipeline optimization, PPA optimization are additionally preferred.
  • Strong RTL design expertise and hands-on experience of Processor/Asic design flow: design, verification, PD synthesis, ECO, bring up.

• Advanced Static Timing: Deep understanding of static timing and its application in chip logic development can be advantageous in driving business results.

• Front-end Processing Expertise: Familiarity with front-end processing and its role in chip logic development can be valuable in shaping the future of cognitive systems logic design.

• Post-Si debug: Familiarity with Post-Si debugs is preferable.

• Performance & Power Analysis: Familiarity with analysing Performance & Power Tools data and coming up with features solving PPA issues.

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