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Open nowPosted 6 days ago

Physical ASIC Design Implementation Engineer

imec

Where
Leuven, Belgium
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Your applicationOpen nowPhysical ASIC Design Implementation Engineerimec · Leuven, Belgium

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  5. 35.6%30 days
  6. 58.0%60 days
This job: posted 6 days ago

The posting

Als Physical ASIC Design Engineer binnen DSRD sta je rechtstreeks in contact met onze klanten voor toekomstige projecten. Je hebt een grondige kennis van de volledige Cadence Innovus Place & Route-flow.

Wat ga je doen?

Al meer dan 25 jaar biedt imec ASIC-prototyping- en productiediensten aan bedrijven over de hele wereld. Imec ondersteunt klanten bij het ontwerpen van geïntegreerde schakelingen (chips) en helpt hen om hun ontwerp van de prototypefase naar productie te brengen. Tot onze klanten behoren meer dan 900 universiteiten en bedrijven wereldwijd.

Om onze groep voor fysieke digitale implementatie (Back-End group) binnen DSRD verder uit te breiden, zijn we op zoek naar een sterk gemotiveerde engineer.

DSRD, als onderdeel van imec, beschikt over uitgebreide industriële ervaring, contacten met toonaangevende foundries en langdurige samenwerkingen met alle belangrijke leveranciers van EDA-tools en IP. Deze unit ondersteunt klanten wereldwijd bij de layout, prototyping, fabricage en het testen van geavanceerde elektronische producten.

Als Physical ASIC Design Engineer binnen DSRD sta je rechtstreeks in contact met onze klanten voor toekomstige projecten. Je hebt een grondige kennis van de volledige Cadence Innovus Place & Route-flow:

  • De flow opzetten voor de specifieke library set en foundry node die worden gebruikt
  • Low-power designs opzetten (UPF)
  • Floorplanning en power grid design
  • Gedetailleerde timing-driven placement
  • STA en eventuele designoptimalisatie voor setup
  • Clock Tree Synthesis
  • Scan chains opnieuw verbinden
  • Gedetailleerde timing-driven routing, inclusief SI
  • IPO’s (in-place optimization) uitvoeren om ervoor te zorgen dat de timing in alle corners correct is
  • Setup- en hold-violations oplossen
  • Sign-off extraction (SPEF/QUANTUS)
  • Sign-off timing (TEMPUS)
  • Sign-off power analysis (VOLTUS)
  • Physical verification (DRC, ERC, LVS, ANT)
  • Logic equivalence checks uitvoeren

Voor hiërarchische designs kun je de leiding nemen over de partitionering en het SDC-bestand op topniveau opsplitsen in timing budget requirements/constraints voor de sub-blocks.

Gedurende de volledige chipdesigncyclus werk je rechtstreeks samen met het Physical Design Implementation-team om de sign-off closure voor tape-out te realiseren. Daarnaast ben je het technische aanspreekpunt voor de klant om de specificaties te bespreken.

Wie ben jij?

  • Je hebt een masterdiploma in elektronica.
  • Je hebt minstens 8 jaar ervaring met physical implementation in geavanceerde technologieknooppunten (12-5 nm) en met hiërarchische designs.
  • Je hebt ervaring met technieken voor het verlagen van het energieverbruik, zoals gated clocks, voltage domains, memory retention en het uitschakelen van power domains.
  • Je hebt ervaring met het debuggen en oplossen van problemen met tools, flows en designs.
  • Je beschikt over uitstekende communicatieve vaardigheden. Een goede kennis van het Engels is een vereiste en je kunt goed samenwerken binnen een internationaal team.
  • Je vindt het leuk om rechtstreeks met klanten samen te werken.

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