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Staff EMIB-T Substrate Yield Engineer

Intel540 open roles

Where
US Arizona Phoenix
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Your applicationOpen nowStaff EMIB-T Substrate Yield EngineerIntel · US Arizona Phoenix

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The clock on this job

Early applications get read.

8.0% of postings close within 7 days. Measured by our own scanner across the market. Intel postings stay open a median of 23 days.

Share of postings closed within
  1. 1.6%1 day
  2. 3.6%3 days
  3. 8.0%7 days
  4. 15.0%14 days
  5. 34.2%30 days
This job: posted today

Intel median: 23 days open

The posting

Job Details:

Job Description:

Intel's APTM organization is seeking a highly driven Staff Technology Development Substrate Yield Lead to drive supplier yield, defect reduction, technical issue closure, and process-control maturity supporting next-generation EMIB-T substrates across Japan suppliers. The team will be chartered to lead yield performance for next-generation advanced packaging technologies, including EMIB-T (Embedded Multi-die Interconnect Bridge with TSV), Intel's most advanced platform for heterogeneous integration partnering with substrate suppliers locally at the HVM factories. This is a high-visibility, high-accountability role with significant responsibility for enabling successful technology development and manufacturing readiness across both Intel Foundry Services (IFS) and Intel Product Groups (IPG).

The ideal candidate is a self-starter who thrives in ambiguous and fast-paced environments, proactively drives issues to closure, and requires minimal supervision. Success in this role requires strong technical depth, urgency in execution, the ability to influence cross-functional teams and suppliers, and a relentless focus on delivering yield and program milestones.

This position requires an Expat assignment in Japan.

Key responsibilities

  • Own day-to-day yield performance and issue closure for assigned supplier lines, modules, products, or process areas.
  • Lead structured investigations from containment and hypothesis development through experiments, failure analysis, corrective action, and sustainment.
  • Use statistical and spatial analytics to identify signatures by line, tool, material, panel position, geometry, product, and time.
  • Establish clear supplier actions, owners, completion criteria, control limits, and verification plans.
  • Support DFM/DFY, qualification, ramp readiness, change control, and deployment of dashboards or automated analytics.
  • Capture reusable learning and communicate facts, hypotheses, decisions, and residual risks clearly.

Behavioral traits

  • Strong analytical and problem-solving skills with the ability to make data-driven decisions in complex environments.
  • Experience working across multiple organizations and influencing stakeholders to achieve results.
  • Demonstrated ability to independently manage complex technical issues, execute with urgency, and drive actions to closure.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates. This position is not eligible for Intel immigration sponsorship

Minimum Qualifications

  • Bachelor's degree with +8 years of experience in Engineering, Materials Science, Physics, Chemistry, Data Science, or a related technical discipline, OR Master's degree with 6+years, OR PhD with 4+years.
  • 5+ years of experience in:Semiconductor manufacturing, advanced packaging, substrate technology, yield engineering, process engineering, or a closely related field. Hands-on experience in substrate, advanced packaging, or semiconductor yield engineering, including statistical analysis, defect reduction, process optimization, SPC, DFM/DFY, defect metrology, failure analysis, and HVM execution. Experience developing or deploying yield monitoring systems, automated analytics, dashboards, image analytics, computer vision, AI/ML-based defect detection, or automated defect classification systems.

Preferred Qualifications:

  • Experience working directly with substrate suppliers and external manufacturing partners.
  • Demonstrated program leadership experience, including coordinating cross-functional technical teams and driving execution in high-visibility, high-impact environments.
  • Experience with semi-additive processing, build-up films, microvias, copper plating, lithography, lamination, embedded silicon, TSV, 2.5D/3D packaging, or heterogeneous integration.
  • Prior experience supporting technology development, qualification, and manufacturing ramp of advanced semiconductor technologies.
  • Experience with automated data pipelines, dashboards, image analytics, computer vision, AI/ML defect detection, or automated defect classification.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

US, New Mexico, Albuquerque, US, Oregon, Hillsboro

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $180,770.00-255,200.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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