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Open nowPosted today

Sr. Staff Validation Engineer

Marvell230 open roles

Where
Santa Clara, CA
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Your applicationOpen nowSr. Staff Validation EngineerMarvell · Santa Clara, CA

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The clock on this job

Early applications get read.

9.5% of postings close within 7 days. Measured by our own scanner across the market. Marvell postings stay open a median of 32 days.

Share of postings closed within
  1. 1.8%1 day
  2. 4.0%3 days
  3. 9.5%7 days
  4. 15.6%14 days
  5. 33.9%30 days
This job: posted today

Marvell median: 32 days open

The posting

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Senior Staff Validation Engineer will drive hands-on lab validation and test execution for advanced ASIC/SoC products integrating CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes. This role is the execution engine of the validation effort. It turns test plans into measurable silicon results through direct silicon bring-up, systematic debug, and rigorous characterization on the bench. The engineer's impact shows up in faster bring-up, earlier discovery of silicon and system-level issues, and high-confidence data that supports product readiness decisions. Working closely with design, DFT, firmware, and product/test engineering, they drive issues from first observation to root cause and resolution. They also develop and maintain the automation, test content, and lab infrastructure that make validation repeatable and scalable, and they mentor engineers on lab best practices and debug methodology.

What You Can Expect

  • Execute silicon bring-up and validation test plans for ASIC/SoC products with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes interfaces.
  • Set up and maintain lab test environments, including boards, power supplies, clocks, resets, and cabling, to ensure stable and repeatable measurements.
  • Operate lab equipment such as oscilloscopes, logic analyzers, protocol analyzers (PCIe/CXL), pattern generators, BERTs, power supplies, and environmental chambers.
  • Develop and use scripts (Python, TCL, shell, MATLAB or similar) for lab automation and data collection/analysis.
  • Run experiments to characterize link and memory behavior (e.g., throughput, latency, BER, margins, power) and summarize results.
  • Assist in debugging issues across silicon, firmware, board, and test setup; capture logs, traces, and measurement data for senior engineers.
  • Document test procedures, lab setups, and results; provide clear, concise updates to the validation lead and cross-functional teams.
  • Contribute feedback to improve test plans, lab infrastructure, and validation processes.

What We're Looking For

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience
  • 3+ years of experience in silicon or system validation, hardware test, or related lab-based roles.
  • Working knowledge of high-speed interfaces and memory subsystems (e.g., PCIe, CXL, DDR, HBM, SerDes concepts).
  • Hands-on experience with lab instruments (oscilloscope, logic analyzer, protocol analyzer, power supplies, etc.).
  • Experience with at least one scripting language used in lab environments (e.g., Python, TCL, shell).
  • Strong problem-solving skills and attention to detail in executing tests and recording results.

Preferred Qualifications

  • Experience with validation or test of high-speed digital interfaces (PCIe, CXL, DDR, HBM or SerDes-based links).
  • Exposure to first silicon bring-up or early hardware prototyping.
  • Familiarity with version control and issue tracking tools used in engineering

Expected Base Pay Range (USD)

127,630 - 191,200, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.


This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.


Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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