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Open nowFirst seen 3 hours ago

ASIC Engineering Intern, Design Verification (Silicon Engineering)

Meta1,114 open roles

Where
Sunnyvale, CA
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Your applicationOpen nowASIC Engineering Intern, Design Verification (Silicon Engineering)Meta · Sunnyvale, CA

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The clock on this job

Early applications get read.

9.6% of postings close within 7 days. Measured by our own scanner across the market. Meta postings stay open a median of 35 days.

Share of postings closed within
  1. 1.9%1 day
  2. 3.9%3 days
  3. 9.6%7 days
  4. 15.6%14 days
  5. 33.9%30 days
This job: first seen 3 hours ago

Meta median: 35 days open

The posting

We are a team of engineers building the silicon IP that powers Augmented Reality (AR) glasses. Our focus is digital design for computer vision and image signal processing: high-performance, low-power hardware that fits into the tight power and space budget of a pair of eyeglasses. Our IP ships in several chips, and our roadmap covers products that will reach the market years from now.

Meta is looking for a Design Verification intern to join our Silicon Accelerators team. You'll work with design, verification, and methodology engineers to verify vision and image-processing IP. You'll write test benches, plan and run tests, and track down bugs in both the design and the test environment. We're looking for someone who likes breaking things and figuring out why they broke. The internship is meant to give you real, production-level DV experience so you're ready to join full-time as a University Grad Design Verification Engineer.

Responsibilities

  • Write SystemVerilog test benches and tests that verify digital IP blocks in computer vision and image signal processing pipelines
  • Build and extend UVM-based verification components (sequences, drivers, monitors, scoreboards) under the guidance of senior engineers
  • Read design specifications and help write verification test plans, including stimulus, checks, and coverage goals
  • Run simulations, debug failures, and work out whether each bug is in the design (RTL) or the test bench
  • Track functional and code coverage, and write directed and constrained-random tests to close coverage gaps
  • Write Python scripts to automate regressions, triage results, and improve verification workflows
  • Work with design and methodology engineers, and present your results in team reviews

Minimum Qualifications

  • Currently has, or is in the process of obtaining, a Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
  • Coursework or project experience in digital logic design: logic gates, flip-flops, finite state machines, timing, and clock domains
  • Experience with Verilog or SystemVerilog through coursework, labs, or projects
  • Programming experience in an object-oriented language (e.g., SystemVerilog classes, C++, Python, or Java)
  • Scripting experience in Python
  • Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment
  • Intent to return to full-time degree program after completion of the internship

Preferred Qualifications

  • Exposure to UVM (Universal Verification Methodology) or another class-based verification methodology
  • Familiarity with verification concepts such as constrained-random stimulus, functional coverage, assertions (SVA), and scoreboarding
  • Coursework or projects in image processing, computer vision, signal processing, or AI/ML hardware acceleration
  • Hands-on experience with an RTL simulator (e.g., VCS, Xcelium, Questa, or Verilator) and waveform debugging
  • Knowledge of data structures and algorithms
  • A completed digital design or verification project, such as a processor, memory controller, bus or communication interface, or FPGA design
  • Strong debugging instincts, curiosity, and clear communication

US: $6,660/month to $12,014/month

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