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Open nowFirst seen 3 hours ago

Machine Learning ASIC Power Architect

Meta1,336 open roles

Pay
$178,000 – $250,000 a year
Where
Sunnyvale, CA
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Your applicationOpen nowMachine Learning ASIC Power ArchitectMeta · Sunnyvale, CA

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The clock on this job

Early applications get read.

13.8% of postings close within 7 days. Measured by our own scanner across the market. Meta postings stay open a median of 35 days.

Share of postings closed within
  1. 2.2%1 day
  2. 4.7%3 days
  3. 13.8%7 days
  4. 22.3%14 days
  5. 37.8%30 days
  6. 59.0%60 days
This job: first seen 3 hours ago

Meta median: 35 days open

The posting

Reality Labs focuses on delivering Meta's vision through creating advanced Augmented Reality AI-enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. Reality Labs Silicon team is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual worlds will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.

In this role, you will define and drive the power architecture of ML accelerators for AR/AI wearables. You'll partner with ML architects, algorithms and software teams, and front-end and back-end designers to set power targets, make architecture trade-offs, and develop methodologies that deliver optimized power, performance, and area (PPA) in advanced technology nodes.

Responsibilities

  • Own power architecture and modeling for ML accelerator IP, from early concept through tape-out and post-silicon correlation
  • Build workload-driven power models (energy per op and per byte moved) to evaluate dataflow, memory hierarchy, precision, and sparsity trade-offs before RTL. Deliver cost/benefit analyses that guide architecture decisions
  • Define power management strategy (clock and power gating, DVFS, retention, power states) and set IP-level power budgets aligned with system battery and thermal targets
  • Drive hardware-software co-design with ML algorithm, compiler, and firmware teams to optimize power across real use cases
  • Establish RTL and gate-level power analysis methodology and guide design teams through power optimization
  • Lead post-silicon power measurement and correlation, and feed what you learn back into models and future architectures
  • Provide technical leadership and mentorship across silicon, systems, and platform teams. Take concepts from prototypes through high-volume consumer products

Minimum Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of experience in power architecture, modeling, or analysis for production silicon
  • Experience building IP and SoC use-case power models and defining IP-level power targets with design owners
  • Understanding of low-power design techniques and power trade-offs across architecture, RTL, and physical implementation
  • Experience with power analysis tools (e.g., PrimeTime, PT WX, PowerArtist, Joules)
  • Proficiency in scripting (e.g., Python, TCL, or Perl)
  • Experience debugging and resolving cross-disciplinary system issues using data-driven methods
  • Bachelor's degree in EE, CE, CS, or a related field, or equivalent practical experience

Preferred Qualifications

  • Experience with AI/ML accelerator architecture and optimizing data flow and memory hierarchy for on-device neural network inference
  • Experience with silicon power measurement and model-to-hardware correlation
  • Master's or Ph.D. in EE, CE, CS, or a related field
  • Experience with mobile, wearable, or battery-powered System-on-Chip (SoCs)
  • Experience with implementation tools (Fusion Compiler, ICC2, Innovus) in advanced nodes

US: $178,000/year to $250,000/year + bonus + equity

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