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Open nowPosted today

Senior Research Engineer I, Adv Pkg, IME

MyCareersFuture97,045 open roles

Pay
SGD 4,500 – SGD 9,000 a month
Where
West, Singapore
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Your applicationOpen nowSenior Research Engineer I, Adv Pkg, IMEMyCareersFuture · West, Singapore

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The clock on this job

Early applications get read.

8.1% of postings close within 7 days. Measured by our own scanner across the market. MyCareersFuture postings stay open a median of 3 days.

Share of postings closed within
  1. 1.7%1 day
  2. 3.6%3 days
  3. 8.1%7 days
  4. 15.1%14 days
  5. 34.0%30 days
This job: posted today

MyCareersFuture median: 3 days open

The posting

  • Process integration development for high density multi-chip fan-out wafer level packaging for various applications such as AI/ HPC, Co-package Optics, Power devices etc.
  • Drive the development of new capabilities such as fine pitch RDL, micro bumping, multi-layer RDL, polymer damascene etc required for future FOWLP integration.
  • Establish novel RDL-first and mold-first fan-out packaging integration flows to meet industry partners requirements for various applications.
  • Plan short loops and work with process module team to develop various processes and materials evaluation for FOWLP.
  • Work with industry partners and multidisciplinary team members to execute the projects/assigned tasks by resolving issues.
  • Conduct engineering experiments for process characterization to drive quality and yield improvements.
  • Coordinate and support engineering build using developed packaging processes and integration.
  • Lead industry and internal capability development projects with manageable risks and mentor less experienced colleagues.
  • Inspire and mentor young talent in semiconductor technology, contributing to workforce development in the field.
  • Publish new findings and technological advancement in prestigious journals and overseas/local conferences.

Job Requirements:

  • Bachelors/Masters in Materials Science and Engineering, Mechanical or Chemical Engineering, Electronics, Electrical and Computer Engineering, or Diploma holder with any engineering or science related field.
  • 5 to 10 years of experience in any semiconductor devices fabrication process integration, and experience in wafer level bumping, RDL and fan-out wafer level package integration will be added advantage.
  • Hands-on experience in semiconductor manufacturing processes such as lithography, plating, etching as well as RDL and bumping process integration.
  • Knowledge of wafer level fabrication processes and advanced packaging technologies, methodologies, and reliability characterization is preferable, but not mandatory.
  • Strong analytical and problem-solving skills. Proficiency in data analysis and interpretation and design of experiments.
  • Excellent written and verbal communication abilities.
  • Ability to work collaboratively in a research-oriented environment (OEMs, customers, and Internal stakeholders). Demonstrated ability to manage multiple tasks and projects simultaneously.
  • Demonstrated expertise in heterogeneous integration, FOWLP technologies, and advanced packaging processes.
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