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Open nowPosted today

Senior Staff Systems Validation Engineer

MyCareersFuture94,660 open roles

Pay
SGD 7,500 – SGD 15,000 a month
Where
Central, Singapore
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Your applicationOpen nowSenior Staff Systems Validation EngineerMyCareersFuture · Central, Singapore

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The clock on this job

Early applications get read.

8.0% of postings close within 7 days. Measured by our own scanner across the market. MyCareersFuture postings stay open a median of 3 days.

Share of postings closed within
  1. 1.6%1 day
  2. 3.5%3 days
  3. 8.0%7 days
  4. 14.9%14 days
  5. 34.1%30 days
This job: posted today

MyCareersFuture median: 3 days open

The posting

Job Responsibilities:-

  • Own PCIe validation strategy and execution for the Storage Accelerator products across pre-silicon and post-silicon phases
  • Define coverage plans including protocol, link, PHY, power management, and compliance scenarios
  • Lead PCIe link bring-up, training, and tuning across multiple generations (Gen3/4/5/6)
  • Perform deep debug using protocol analyzers, oscilloscopes, and logic analyzers
  • Drive PCI-SIG compliance testing including electrical and protocol validation
  • Ensure interoperability with server CPUs from leading manufacturers
  • Develop and enhance automation frameworks (Python, C/C++) for validation scalability
  • Own and manage Functional Circuit Test (FCT) and In-Circuit Test (ICT) processes
  • Lead RMA analysis and work closely with customers and manufacturing teams to resolve board-level issues
  • Work closely with Architecture, Design, Software and Signal integrity teams
  • Coordinate Test program and test automation scripts development
  • Coaching Junior Engineering staff

Job Requirements:-

  • Bachelor Degree or Master’s and above in Computer Engineering, Electrical/Electronics Engineering, or related field with at least 12 years or above of working experience in silicon validation or system validation with strong PCIe focus
  • Experienced with system validation in complex SoC (System on Chip) environment
  • Deep understanding of: PCIe protocol stack (Transaction, Data Link, Physical layers), PCIe power management, Link training and equalization
  • Hands-on experience with PCIe analysers. Scopes and signal integrity tools
  • Strong debugging skills in Hardware/Software co-debug
  • Experience with high speed Serdes tuning and validation methodologies
  • Familiar with system board design/debugging and usage of lab equipment like Oscilloscope and Logic analyzer
  • Good understanding in high-speed interface system/electrical verification & validation
  • Experience of C/C++ Programming and other test script development languages
  • In-depth expertise of PCIe Gen3/Gen4/Gen5
  • Storage/Networking domain expertise is highly desirable
  • Knowledge of state-of-the-art data compression and cryptographic algorithms

Location: Next to Bendemeer MRT

Interested candidatesmay submit detailed CV with the following info:-

  • Current salary, including AWS or Variable Bonus
  • Expected salary
  • Availability
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