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Open nowPosted 4 days ago

Staff ASIC Design Engineer

Nokia576 open roles

Where
United States
Work mode
Hybrid
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Your applicationOpen nowStaff ASIC Design EngineerNokia · United States

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The clock on this job

Early applications get read.

13.7% of postings close within 7 days. Measured by our own scanner across the market. Nokia postings stay open a median of 14 days.

Share of postings closed within
  1. 2.3%1 day
  2. 4.8%3 days
  3. 13.7%7 days
  4. 22.1%14 days
  5. 37.6%30 days
  6. 59.1%60 days
This job: posted 4 days ago

Nokia median: 14 days open

The posting

Job Description

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise​

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.​

Nokia is seeking a Senior/Staff High-Speed Analog IC Design R&D Engineer to create innovative products in a fast-paced and collaborative team environment. The engineer will be hands-on with all phases of R&D including product definition, circuit design, layout, verification, bring-up, DVT, qualification, test and production ramp-up. As a member of a vertically-integrated team, the engineer will be directly supporting system level customers and will be closely working with product, operations and reliability teams. The self-motivated engineer must be able to anticipate problems and devise effective solutions.

NION2026

Responsibilities

  • Responsible for developing > 100Gbaud ICs for future generation products
  • In charge of many aspects of IC product development, such as design, layout, and bring-up.
  • Work closely with verification, CAD, product and test engineering teams to devise and conduct DVT plans and characterization.

Qualifications

Minimum Experience Requirements:

  • Experience with High-speed analog IC designs with SiGe BiCMOS or CMOS
  • Knowledge of transmission lines and other high-frequency passive structures
  • A good understanding of device physics and impact on analog circuits and techniques to improve performance.
  • Experience with RF wafer probing, lab equipment and evaluation of high-speed analog ICs
  • Familiarity with VerilogA and CAD scripting languages (Skill, python, shell scripts) would be an asset.
  • Must be a team player with good verbal and written communication skills

Education Requirements:

  • BS 5+ years – MS/PhD preferred
  • MS 3+ years
  • PhD
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