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ASIC Clocks Verification Engineer - New College Grad 2026

NVIDIA2,522 open roles

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US, CA, Santa Clara
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Your applicationOpen nowASIC Clocks Verification Engineer - New College Grad 2026NVIDIA · US, CA, Santa Clara
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The clock on this job

Early applications get read.

8.3% of postings close within 7 days. Measured by our own scanner across the market. NVIDIA postings stay open a median of 28 days.

Share of postings closed within
  1. 1.9%1 day
  2. 4.0%3 days
  3. 8.3%7 days
  4. 15.3%14 days
  5. 34.2%30 days
This job: posted today

NVIDIA median: 28 days open

The posting

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today.

The GPU clocks group is looking for an exceptional ASIC Clocks Verification Engineer. The team is responsible for crafting all aspects of GPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back-end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab.

What you'll be doing:

  • As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to verify high frequency clock structures.
  • Be able to engage with multiple teams and design the GPU clock structure to satisfy all the architectural constraints.
  • Your understanding of general verification principles will be valuable to verify the clocks design.
  • Together with other team members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl to improve the productivity of the above teams.
  • Collaborate with Software and product group to debug GPU clock silicon bugs in our new products.
  • Understand and design clocking structures to overcome sub-micron design challenges.
  • You will also identify improvements in the current design and propose and implement new ways to improve the efficiency in the GPU clocking design.

What we need to see:

  • A Master’s degree in Electrical Engineering (or equivalent experience).
  • Practical experience with SystemVerilog and Universal Verification Method (UVM).
  • Experience with Design Verification, Logic Design, and Logic Synthesis.
  • Strong coding skills in Python, Perl, or other industry-standard scripting languages.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? If so, we want to hear from you.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 13, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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