The posting
ABOUT OLIX
AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.
THE ROLE:
At OLIX, the performance of our technology depends not only on silicon design, but on how effectively that silicon is packaged, integrated, and scaled into products. Packaging is a first-class element of our rack-scale co-design philosophy, and over successive product generations it will become one of our most important sources of system-level differentiation.
The Advanced Packaging Architect will own OLIX's packaging technology direction: defining the packaging architecture and roadmap across current and future products, and delivering the packaging solutions that turn our ASICs into high-performance systems.
The DX-1 provides the foundation, with a well-bounded packaging scope that must be executed to a high standard on an aggressive schedule. Beyond DX-1, our roadmap moves rapidly toward significantly more advanced packaging, with the potential for denser multi-die and chiplet-style integration, 2.5D and 3D architectures, and progressively more advanced optical integration. This role shapes that trajectory and lays the foundation for future products that will fast-follow DX-1.
This is a high-impact role combining hands-on engineering with architectural and strategic ownership. You will lead packaging across the full development flow for DX-1, including package architecture, detailed design, layout, simulation, and product readiness, while simultaneously defining the packaging technology strategy, partner ecosystem, and internal capability that future generations will require. As the programme scales, you will have the opportunity to build the packaging function and team around you.
RESPONSIBILITIES:
Advanced Package Architecture & Design
- Own package architecture and design for ASIC-to-substrate integration, including bump/pad mapping, substrate escape, interconnect strategy, package floorplanning, and stack-up definition
- Lead the development of 2.5D and 3D package architectures for future OLIX product variants, including multi-die integration, chiplet-style interfaces, and heterogeneous integration approaches
- Define package structures that meet electrical, thermal, mechanical, reliability, and manufacturability requirements
- Translate silicon and system requirements into practical package design rules, routing constraints, and implementation strategies
Full Package Design Flow
- Own or direct the full package design flow, from concept definition through detailed design, analysis, layout, verification, release, and manufacturing support
- Develop and review package layouts including die placement, substrate routing, power/ground distribution, high-speed interface breakout, and physical integration constraints
- Own or direct PI/SI simulation activities to validate signal integrity, power delivery, and package performance, translating results directly into design improvements and sign-off decisions
- Support package-to-board co-design, including substrate layout and PCB layout/interface definition where required
- Ensure strong alignment between die, package, substrate, and board-level implementation
- Oversee package database management, design reviews, sign-off, and release readiness
Capability & Team Building
- Establish OLIX's packaging engineering capability: methodologies, design libraries, templates, rules, tool flows, and workflows that support efficient and repeatable development across product generations
- Define the hiring roadmap for the packaging function and, as the programme scales, build and lead a team of packaging engineers while remaining a hands-on technical contributor
- Mentor engineers across adjacent disciplines on packaging-aware design practices
- Support tool flow development and integration across package, substrate, simulation, and PCB environments
Cross-Functional Engineering
- Work closely with ASIC, optics, mechanical, thermal, and systems engineers to optimise package performance and system integration
- Collaborate with substrate vendors, OSATs, foundries, and external partners on stack-ups, design rules, implementation feasibility, and manufacturing readiness
- Ensure package design decisions support broader product requirements including manufacturability, reliability, serviceability, and scale
- Act as the key interface between package design and adjacent engineering domains
Manufacturing & Productisation Support
- Ensure package designs are aligned with assembly, qualification, reliability, and manufacturing requirements
- Lead DFM/DFX activities for advanced package technologies and substrate implementations
- Support prototype build, bring-up, qualification, and early production with strong technical ownership of packaging-related issues
- Participate in root cause analysis and corrective action for packaging or integration issues identified during build, test, or reliability assessment
- Review substrate deliverables, fabrication outputs, and manufacturing documentation for completeness and technical quality
SKILLS & EXPERIENCE
- 10+ years' experience in advanced semiconductor packaging for ASIC or other high-performance products
- Demonstrated ownership of packaging architecture, technology strategy, or roadmap development for complex products
- Deep expertise in front-end package design, including ASIC-to-substrate integration
- Strong experience with 2.5D and/or 3D package architectures, including multi-die and heterogeneous integration
- Strong hands-on capability with package design tools such as Cadence Allegro X APD, Siemens Xpedition, or equivalent
- Experience leading package development across layout, simulation, verification, and release
- Strong PI/SI simulation capability, including package-level signal integrity and power delivery analysis using tools such as Ansys SIwave, Cadence Sigrity, or equivalent
- Experience in substrate design and package-to-board integration
- Experience building packaging capability, processes, or teams, or leading engineers while remaining a hands-on contributor
- Strong working relationships with substrate vendors, OSATs, and foundry packaging organisations
- Good understanding of manufacturability, interconnect technologies, and package reliability
- Strong technical judgement, communication, and problem-solving skills
- Degree in a relevant engineering or physical sciences discipline
DESIRABLE
- Experience with AI accelerators, high-performance compute, networking, or advanced data-centre hardware
- Familiarity with wafer-level packaging and emerging advanced packaging platforms
- Exposure to optical or photonic integration with electronic packaging
- Familiarity with package reliability, qualification, and failure analysis workflows
- Exposure to new product introduction and scaling advanced package technologies into production
COMPENSATION & EQUITY
- Competitive Salary: commensurate with your experience, skills, and location.
- Equity & Ownership: Meaningful stock options. You're not just joining the mission; you're owning a piece of it.
- Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office.
