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Open nowPosted 92 days ago

FPGA Verification Engineer, Air Dominance and Strike (Fastwater Staffing)

Recruiting301 open roles

Where
Costa Mesa, California, United States
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Your applicationOpen nowFPGA Verification Engineer, Air Dominance and Strike (Fastwater Staffing)Recruiting · Costa Mesa, California, United States

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The clock on this job

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8.0% of postings close within 7 days. Measured by our own scanner across the market.

Share of postings closed within
  1. 1.6%1 day
  2. 3.6%3 days
  3. 8.0%7 days
  4. 15.0%14 days
  5. 34.2%30 days
This job: posted 92 days ago

The posting

WHAT YOU’LL DO

  • Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs
  • Develop verification plans with traceability to system and hardware requirements
  • Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks
  • Build functional coverage models and drive code coverage analysis to closure
  • Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs
  • Establish and maintain regression suites, tracking coverage metrics and verification progress
  • Debug failures using waveform tools and simulation logs at the HDL and system level
  • Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement
  • Support hardware validation and board bring-up on target platforms
  • Ensure verification meets DO-254 and relevant safety standards
  • Author verification closure reports and coverage analysis summaries

REQUIRED QUALIFICATIONS

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
  • 2+ years of experience in FPGA/ASIC verification
  • Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches
  • Object-oriented programming principles
  • Industry simulators (Questa, VCS, Xcelium, or Vivado)
  • Git-based collaborative workflows including code review
  • Linux development environments
  • Strong communication and teamwork skills
  • Eligible to obtain and hold a U.S. Secret security clearance

PREFERRED QUALIFICATIONS

  • 5+ years of experience in FPGA/ASIC verification
  • Master’s degree in Electrical Engineering, Computer Engineering, or related field
  • DO-254, avionics verification standards for UAS, and safety-critical verification processes
  • SVUnit or equivalent unit-testing frameworks
  • Formal verification or CDC verification tools
  • Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI
  • Verification automation scripting (Python, Tcl, Makefile)
  • SoC and ARM-based embedded platforms
  • Verification automation, CI/CD integration, and Nix-based build environments
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