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Open nowPosted 25 hours ago

Member of Technical Staff, Post-Training

Ricursive Intelligence15 open roles

Where
Palo Alto
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Your applicationOpen nowMember of Technical Staff, Post-TrainingRicursive Intelligence · Palo Alto
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The clock on this job

Early applications get read.

13.5% of postings close within 7 days. Measured by our own scanner across the market. Ricursive Intelligence postings stay open a median of 60 days.

Share of postings closed within
  1. 2.3%1 day
  2. 4.6%3 days
  3. 13.5%7 days
  4. 21.8%14 days
  5. 36.6%30 days
  6. 58.9%60 days
This job: posted 25 hours ago

Ricursive Intelligence median: 60 days open

The posting

Ricursive Intelligence is a frontier AI lab building self-improving systems, starting with chip design. We are reinventing chip development and closing the loop between AI and the hardware that fuels it, recursively accelerating the path to artificial superintelligence. Backed by $335M from Sequoia, Lightspeed, DST, and NVIDIA Ventures, we are a growing, fast-paced team where every hire shapes the work.

The company has unmatched talent density, including IMO, IPhO, and IOAA gold medalists, pioneers who made prior breakthroughs in chip design: AlphaChip (Nature 2021), ePlace (DAC Best Paper Nominee 2014), RL-CCD (DAC Best Paper 2023), INSTA (DAC Best Paper 2025), and C3PO (ASP-DAC Best Paper 2026), chip leads for Apple Silicon (multiple generations of iPhone and iPad) and Google (TPU, OpenTitan), and top researchers and engineers from Anthropic, Google DeepMind, Stanford, and MIT.

We are looking for the very best post-training researchers and engineers in the world.

A small team trained Ripple-65B Preview https://www.ricursive.com/ripple from scratch and set a new U.S. open-weight state-of-the-art on agentic coding (80.5 on TerminalBench 2.1), outperforming U.S. open-weight models up to 15x larger at one-tenth the cost of the previous open-weight SOTA. We built our own synthetic data pipelines instead of buying post-training data, and reached state-of-the-art with 1.4M rollouts, roughly 70x fewer than the prior SOTA.

You will contribute to core pieces of post-training, from synthetic data to RL environments to evaluation, and your work will show up directly in the model. We built Ripple to start closing the loop between models and the chips they run on. Few teams work at this intersection, and we've only scratched the surface. As we scale toward the frontier, we are selectively expanding our team of brilliant researchers and engineers.

WHAT YOU WILL DO

- Design and iterate on SFT and RL recipes for large-scale models, with a focus on compute efficiency and steep, stable RL climbs.

- Build and scale synthetic data pipelines, including generation, quality filtering, and coverage metrics.

- Create long-horizon synthetic environments and task curricula for agentic coding and reasoning.

- Make RL stable at scale through careful recipe and stability work.

- Build evaluations that track agentic capability, catch regressions, and drive recipe decisions.

- Own experiments end to end on large GPU clusters: design, launch, debug, and analyze runs.

- Partner with teammates to make post-training efficient on our training and serving platforms.

MINIMUM QUALIFICATIONS

- Degree in CS, EE, math, or a related field, or equivalent practical experience.

- Hands-on post-training experience (SFT, RL, synthetic data and environments) at a frontier AI lab or equivalent.

- Deep fundamentals in transformer internals and distributed training.

PREFERRED QUALIFICATIONS

- Research track record in RL, NLP, or machine learning, such as publications at NeurIPS, ICML, ICLR, or COLM.

- Experience building RL environments for complex frontier coding and agentic benchmarks.

- A shipped result: a post-training run, data recipe, model release, or research outcome that moved a benchmark or product.

- Shipped RL infrastructure, such as async rollouts and inference engines like vLLM or SGLang.

- Experience navigating ambiguity and making design decisions across the stack.

- Interest in applying LLMs to hardware and chip design (no prior experience required).

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