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Open nowPosted 43 days ago

Software Engineer, Chip Design

Ricursive Intelligence14 open roles

Where
Palo Alto
Work mode
On site
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Your applicationOpen nowSoftware Engineer, Chip DesignRicursive Intelligence · Palo Alto

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The clock on this job

Early applications get read.

11.8% of postings close within 7 days. Measured by our own scanner across the market. Ricursive Intelligence postings stay open a median of 60 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.4%3 days
  3. 11.8%7 days
  4. 18.6%14 days
  5. 35.6%30 days
  6. 45.1%60 days
This job: posted 43 days ago

Ricursive Intelligence median: 60 days open

The posting

Ricursive Intelligence is a frontier AI lab building self-improving systems, starting with chip design. We are reinventing chip development and closing the loop between AI and the hardware that fuels it, recursively accelerating the path to artificial superintelligence. Backed by $335M from Sequoia, Lightspeed, DST, and NVIDIA Ventures, we are a growing, fast-paced team where every hire shapes the work.

The company has unmatched talent density, including IMO, IPHO, and IOAA gold medalists, pioneers who made prior breakthroughs in chip design: AlphaChip (Nature 2021), ePlace (DAC Best Paper Nominee 2014), RL-CCD (DAC Best Paper 2023), INSTA (DAC Best Paper 2025), and C3PO (ASP-DAC Best Paper 2026), chip leads for Apple Silicon (multiple generations of iPhone and iPad) and Google (TPU, OpenTitan), and top researchers and engineers from Anthropic, Google DeepMind, Stanford, and MIT.

ABOUT THE ROLE

As a Software Engineer at Ricursive, you’ll build the systems and infrastructure that power our chip design flow. You’ll work across the broader design stack, improving how we run, evaluate, and iterate on complex problems at scale. This includes building reliable execution infrastructure, developing tooling that connects different stages of the flow, and improving performance and scalability.

You’ll run against real designs with real constraints, debug issues that only emerge at scale, and make engineering tradeoffs around quality, runtime, robustness, and deadlines.

WHAT YOU WILL DO

- Develop and scale the infrastructure behind our chip design flow, optimizing for scalable systems that can support hierarchical design, advanced process nodes, and increasingly complex design constraints.

- Analyze design metrics like timing violations, congestion, routing issues, and other design problems, helping the overall flow converge faster toward better PPA.

- Deploy AI-driven methods to automate design analysis, optimization, and iteration across the flow.

MINIMUM QUALIFICATIONS

- Bachelor’s degree in Computer Science, Electrical Engineering, or a related technical field.

- Strong programming skills in Python, C++, Java, or a comparable language. Comfortable using modern AI-assisted development tools to navigate complex codebases, debug problems, and accelerate engineering workflows.

- Working understanding of the digital chip design flow, including the major stages from RTL through physical design and signoff.

- Demonstrated ability to take ownership of ambiguous technical problems, ramp quickly in unfamiliar areas, and drive work through to production.

PREFERRED QUALIFICATIONS

- Master’s or PhD in Computer Science, Electrical Engineering, or a related technical field.

- Experience with semiconductor design, distributed systems, or optimization.

- Familiarity with design automation algorithms in one or more areas of the chip design flow, such as placement, timing analysis, RC extraction, netlist processing.

- Demonstrated and quantified the PPA benefit of using AI/ML tooling

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