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Open nowPosted 5 days ago

Principal Place and Route (PnR) Engineer

SambaNova71 open roles

Pay
$999,999 a year
Where
Austin, Texas, United States; San Jose, California, United States
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Your applicationOpen nowPrincipal Place and Route (PnR) EngineerSambaNova · Austin, Texas, United States; San Jose, California, United States
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The clock on this job

Early applications get read.

13.3% of postings close within 7 days. Measured by our own scanner across the market. SambaNova postings stay open a median of 63 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.6%3 days
  3. 13.3%7 days
  4. 21.3%14 days
  5. 35.7%30 days
  6. 59.1%60 days
This job: posted 5 days ago

SambaNova median: 63 days open

The posting

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.

About the team

The Place and Route team writes the software that maps dataflow graphs onto SambaNova’s Reconfigurable Dataflow Unit (RDU). Our tools partition each graph, place the pieces on the chip’s compute and memory units, and route the communication between them. The quality of that mapping sets the throughput of the compiled program, including large language model inference and training. We are looking to grow our team with highly motivated engineers who want to utilize advanced algorithms to solve challenging problems.

About the Role

You will develop and tune the partitioning, placement, and routing algorithms that map customer workloads onto the RDU. You will work with the compiler team, hardware architects, and performance engineers to model new hardware constraints and trace throughput gaps back to mapping decisions. Your changes will ship in production releases and show up in measured performance.

Responsibilities

  • Develop partitioning, placement, and routing algorithms that meet hardware resource constraints and keep compile times practical
  • Tune PnR results for target workloads, including LLM inference at different batch sizes and concurrency levels
  • Model new hardware constraints and architecture features in our solvers and heuristics as the chip evolves
  • Analyze compiled output with performance engineers and trace throughput gaps back to mapping decisions
  • Build the infrastructure for prototyping, regression testing, and deployment of PnR changes
  • Work with the compiler and hardware teams to define interfaces and resource models

Required Qualifications

  • M.S. or Ph.D. in Computer Science, Computer Engineering, or related field
  • 3+ years of experience developing optimization or graph algorithms in industry or research
  • Expert knowledge of graph algorithms, partitioning algorithms, combinatorial optimization, or MILP solvers
  • Strong proficiency in C/C++
  • Familiarity with Python
  • Experience designing large, highly parallel, performance-sensitive systems
  • Ability to learn hardware architecture and apply it to improve performance
  • Experience solving NP-hard problems in practice with heuristics, approximation, or pruned exact methods

Preferred Qualifications

  • Experience with place and route for FPGAs, CGRAs, or other spatial architectures
  • Experience with ML compilers such as MLIR, LLVM, TVM, or XLA
  • Experience with simulated annealing, constraint programming, or SAT/SMT solvers
  • Familiarity with LLM inference stacks such as vLLM and PyTorch
  • Publications at venues such as FPGA, DAC, ICCAD, or MLSys

Base Salary Range:

Base Pay Range

$1—$999,999 USD

Submission Guidelines Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.

EEO Policy SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.

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