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Open nowFirst seen 72 days ago

Sr. Manager Verification

Semtech87 open roles

Where
IND - Hyderabad
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Your applicationOpen nowSr. Manager VerificationSemtech · IND - Hyderabad

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The clock on this job

Early applications get read.

12.7% of postings close within 7 days. Measured by our own scanner across the market. Semtech postings stay open a median of 42 days.

Share of postings closed within
  1. 2.2%1 day
  2. 4.5%3 days
  3. 12.7%7 days
  4. 20.4%14 days
  5. 35.6%30 days
  6. 58.7%60 days
This job: first seen 72 days ago

Semtech median: 42 days open

The posting

Responsibilities:

  • Lead, supervise, mentor, and develop a team of verification engineers across multiple projects. Manage verification team deliverables, quality, schedules, and resource allocation for concurrent projects. (20%)
  • Track & report verification progress using quantitative metrics and coverage analysis. Identify and mitigate verification risks early. Report to remote verification & design teams. Coordinate with project management and cross-functional teams. (20%)
  • Drive definition and implementation of comprehensive verification plans and test strategies for digital/mixed-signal integrated circuit designs. Work closely with design teams to understand micro-architecture and functional specifications. Direct detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (20%)
  • Manage design and implementation of complex testbenches using System Verilog and UVM methodology. Lead block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Improve verification scalability and portability from project to project by environment enhancement and tools automation. Establish and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (20%)
  • Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%)
  • Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%)
  • Technical support to silicon lab evaluation, test, product and application engineers. (5%)

Minimum Qualifications:

  • 8+ years of industry experience in integrated circuit design verification (DV)
  • 3+ years in a technical leadership or management role
  • B.S. or M.S. in Electrical or Computer Engineering
  • Proven track record of successful tape-outs for complex digital or mixed-signal designs
  • Demonstration of ability to lead technical teams and drive high-quality & timely results
  • Experience managing concurrent projects, competing priorities and sub-teams
  • Strong analytical, synthesis and problem solving skills
  • In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals.
  • Proficiency in System Verilog as High-level Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Cadence, Siemens)
  • Experience with standard hardware protocols (I2C, I3C, SPI, MIPI)
  • Independent, self-motivated, rigorous, innovating, team player and able to follow through
  • Excellent verbal and written communication skills

Desired Qualifications

  • Knowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modelling, test and application
  • Experience with analog block behavioral modelling with SV RNM/Verilog/VHDL
  • Experience with consumer and/or ITA market circuit developments
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