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Open nowPosted 39 days ago

NoC Design Engineer, Multimedia Lab

TikTok4,303 open roles

Where
San Jose, California, United States of America
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Your applicationOpen nowNoC Design Engineer, Multimedia LabTikTok · San Jose, California, United States of America

  1. YouYes, apply to this one.

  2. CV RocketCV written for this posting.

  3. 25 readersRecruiter, hiring manager, skeptic. Round after round.

  4. CV RocketApplied on TikTok's own form.

The reply lands in your private mailbox

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The clock on this job

Early applications get read.

12.9% of postings close within 7 days. Measured by our own scanner across the market. TikTok postings stay open a median of 20 days.

Share of postings closed within
  1. 2.2%1 day
  2. 4.7%3 days
  3. 12.9%7 days
  4. 21.0%14 days
  5. 35.6%30 days
  6. 58.5%60 days
This job: posted 39 days ago

TikTok median: 20 days open

The posting

Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

Responsibilities: - Responsible for the architecture design, development, implementation, and integration of NoC (Network-on-Chip) systems. - Collaborate with the verification team to ensure the functional correctness and performance targets of the NoC. - Work with the backend/physical implementation team to ensure that the NoC's physical implementation meets design goals.

Minimum Qualification(s) - Bachelor's degree or above in Microelectronics, Computer Science, or a related field; 4+ years of experience in bus/interconnect development. - Solid understanding of computer architecture; experience in large-scale SoC chip design; proficiency in at least one commercial NoC/bus IP, such as FlexNoC or NIC. - Proficiency in common bus protocols, such as AMBA AXI, APB, and AHB. - Strong foundation in logic design and RTL coding; experience with a complete front-end design flow; familiarity with common EDA tools and with Lint, CDC, Synthesis, and STA. - Familiarity with scripting languages commonly used in design flows, such as Python, TCL, and Perl; familiarity with common IPs in SoC systems and with clock/reset design. - Strong logical thinking, communication and presentation skills, and a collaborative team spirit; honest and upright.

Preferred Qualification(s) - Familiarity with the architecture, protocols, and complex data flows of core SoC subsystems (e.g., CPU/NPU clusters, Memory subsystems, NoC). - Hands-on experience with Hardware Emulation (Palladium, ZeBu) or FPGA prototyping platforms. - Proficiency in Formal Verification methodologies and tools (e.g., JasperGold). - Experience in SoC-level Performance and Power-Aware (PA) verification.

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