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Open nowPosted 218 days ago

SI/PI, Package and Power Delivery Engineers

Tylsemi10 open roles

Where
India
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Your applicationOpen nowSI/PI, Package and Power Delivery EngineersTylsemi · India

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  6. 58.1%60 days
This job: posted 218 days ago

The posting

About Tylsemi

Tylsemi is building and scaling high-impact semiconductor operations. We partner across design, manufacturing, and supply chain to bring silicon from concept to high-volume production with speed, quality, and predictable execution.

Role Overview

As an SI/PI, Package and Power Delivery Engineer at Tylsemi, you will own signal integrity, power integrity, and package/PDN co-design across chip, package, and board interfaces. You will work closely with SoC, physical design, analog, package, board, and validation teams to ensure robust high-speed links, stable power delivery, and predictable signoff from early architecture through tapeout and bring-up. This role is open across experience levels (5–20 years) and is ideal for engineers who enjoy cross-domain problem solving and turning complex electrical constraints into clean, manufacturable solutions.

What You’ll Do

  • Drive SI/PI methodology and execution from early planning through signoff for high-speed interfaces and power delivery networks
  • Perform package/board/chip co-design: define stackups, routing constraints, via strategies, reference planes, and return-path integrity
  • Model and analyze high-speed channels (e.g., SerDes, DDR, PCIe, USB, Ethernet) including insertion/return loss, crosstalk, jitter, eye margins, and equalization tradeoffs
  • Build and validate electrical models (IBIS/IBIS-AMI, S-parameters, SPICE) and ensure model correlation and version control hygiene
  • Own PDN design and analysis across die/package/board: impedance targets, decap strategy, anti-resonance mitigation, and rail stability
  • Run PI signoff including DC/AC IR drop, EM, dynamic droop/noise, and power/ground bounce; drive fixes with clear, reviewable action plans
  • Partner with physical design and signoff teams on power grid architecture, bump/ball planning, current density limits, and rail partitioning
  • Collaborate with package engineering on substrate routing, escape, ballout, and manufacturability constraints; review and approve package design deliverables
  • Define and enforce design rules/constraints for routing, spacing, shielding, length matching, and reference plane transitions
  • Support lab bring-up and correlation: translate silicon/package/board measurements into model updates and design improvements
  • Create and maintain automation, checks, and reporting (Python/Tcl or equivalent) to improve predictability, repeatability, and execution speed
  • Contribute to tapeout readiness: documentation, checklists, design reviews, and root-cause analysis to prevent recurrence

What We’re Looking For

  • Hands-on experience delivering SI/PI and package/PDN solutions for complex SoCs (scope aligned to level of experience)
  • Strong fundamentals in transmission lines, S-parameters, impedance, return paths, coupling/crosstalk, and power delivery behavior across frequency
  • Ability to translate system requirements into actionable constraints and to drive closure across multiple teams and design stages
  • Methodical debug skills: clear problem statements, data-driven root cause, and practical mitigation plans
  • Strong communication and engineering hygiene: reproducible analyses, clean documentation, and review-friendly deliverables

Required Skills

  • Signal Integrity (SI) analysis for high-speed interfaces
  • Power Integrity (PI) / PDN design and analysis (chip-package-board)
  • Package and power delivery co-design (substrate/ballout/bumps, stackup and routing constraints)
  • Electrical modeling (S-parameters, SPICE, IBIS/IBIS-AMI) and correlation mindset
  • Cross-functional execution with SoC/PD/analog/package/board/validation teams

Nice to Have

  • Experience with industry tools for SI/PI and package analysis (e.g., HFSS, SIwave, ADS, HSPICE/Spectre, PowerSI, Clarity, Ansys RedHawk/Voltus or equivalents)
  • DDR/LPDDR and SerDes compliance experience (channel budgets, jitter/noise decomposition, margining)
  • Advanced packaging exposure (2.5D/3D, interposers, chiplets, HBM, CoWoS/EMIB-like concepts) and related SI/PI challenges
  • Thermal-awareness in PDN/package decisions and collaboration with thermal/mechanical teams
  • Experience defining signoff criteria, templates, and reusable flows across programs

Success in This Role Looks Like

  • Predictable SI/PI closure with clear milestones, risk tracking, and minimal late-stage surprises
  • Robust package/PDN solutions that meet impedance/noise/jitter targets and scale cleanly to production
  • Fast, high-quality debug and mitigation of SI/PI issues with strong cross-team alignment
  • Well-documented, reproducible analyses and signoff artifacts that improve team velocity and tapeout readiness

Location

  • Bengaluru, India
  • Pune, India

Experience

5–20 years

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