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Open nowPosted 96 days ago

DFT Engineer

Workable (global search)108,016 open roles

Where
Cambridge, England, United Kingdom
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Your applicationOpen nowDFT EngineerWorkable (global search) · Cambridge, England, United Kingdom

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Share of postings closed within
  1. 1.6%1 day
  2. 3.6%3 days
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  4. 14.9%14 days
  5. 34.0%30 days
This job: posted 96 days ago

Workable (global search) median: 7 days open

The posting

Raspberry Pi is seeking a DFT engineer to join our expanding ASIC team to help deliver our next-generation products. We have been building our own silicon at Raspberry Pi for some years now, starting with the RP2040 microcontroller in 2021, and following with the RP1 southbridge chip for the main Raspberry Pi platform on Raspberry Pi 5. Our second-generation microcontroller, RP2350, was released in 2024. The ASIC team looks after everything in the silicon flow, from specification through design, verification, and implementation, including ATE test and qualification. With a small team, we get involved in all aspects of getting successful products into production.

As a DFT Engineer you will be responsible for creating, implementing, and verifying DFT solutions on future Raspberry Pi ASIC designs to ensure quality standards are maintained for products shipping in volume. You will use advanced DFT methods to balance requirements for test coverage, cost, and time to market.

The successful candidate will be:

  • Able to define a suitable DFT strategy at chip, subsystem, and IP level, including structural and functional methods, and make pragmatic trade-offs between methods.
  • Experienced with Tessent DFT tool flow for inserting MBIST, EDT, SSN, scan controls via IJTAG, and IP test using ICL/PDL, in both flat and hierarchical designs.
  • Experienced in verification of DFT structures, and debugging related issues.
  • Able to support DFT through implementation and sign-off, including generating timing constraints and debugging timing, power, and formal equivalence issues.
  • Willing to share knowledge and mentor other members of the team.

Requirements

Key requirements:

  • Experience with IC development flows.
  • Experience with Tessent DFT tools.
  • A good level of understanding of complex IP issues for DFT, including on-chip clocking.
  • Experience in ATPG, MBIST, and simulation debug, including UPF-related issues.
  • Willingness to contribute and share activities with a wider team.
  • Good scripting skills, including TCL.

The following would also be useful:

  • Ability to demonstrate an understanding of advanced silicon technologies and fault models.
  • Familiarity with test access standards, e.g. IJTAG/IEEE1687.
  • Familiarity with vector translation and bring-up on ATE platforms.

In addition, candidates should have:

  • A degree in electronic engineering, computer science, or a related discipline.
  • A proactive approach to troubleshooting.
  • The ability to coach other members of the team.

Benefits

  • Competitive salary based on level of experience
  • Employer pension contributions of 8% when the employee contributes 4% of their gross salary into the salary sacrifice scheme
  • Life assurance of 4 × base salary
  • Income protection of 75% of base salary in the event of critical illness, commencing after 13 weeks of long-term illness or absence from work
  • Private medical insurance (medical history disregarded)
  • Access to our electric vehicle salary sacrifice scheme, subject to eligibility
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