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Open nowPosted 33 days ago

Mixed Signal Design Verification Engineer

Allegro MicroSystems65 open roles

Where
Prague, Czech Republic
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Your applicationOpen nowMixed Signal Design Verification EngineerAllegro MicroSystems · Prague, Czech Republic

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The clock on this job

Early applications get read.

11.8% of postings close within 7 days. Measured by our own scanner across the market. Allegro MicroSystems postings stay open a median of 41 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.4%3 days
  3. 11.8%7 days
  4. 18.6%14 days
  5. 35.6%30 days
  6. 45.1%60 days
This job: posted 33 days ago

Allegro MicroSystems median: 41 days open

The posting

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve.

The Opportunity

Allegro MicroSystems is seeking an enthusiastic and motivated Mixed-Signal Design Verification (MSDV) Engineer to join our development team. In this role, you will work under the guidance of senior technical leads to develop and execute top-level mixed-signal verification testbenches for our market-leading automotive and industrial integrated circuits. You will act as a key interface between transistor-level analog building blocks and digital control systems, running functional simulations across power sequencing, register configurations, and system-level testcases to ensure first-pass silicon success.

What You Will Do

  • Run and debug top-level AMS simulations using Cadence AMS Designer and Virtuoso to verify chip-level interactions between analog front-ends and digital logic.
  • Assist in writing and maintaining behavioral models and testbenches using Verilog, SystemVerilog, and Verilog-AMS/Real-Number Modeling (RNM/wreal).
  • Verify power-up/power-down sequences, brown-out events, and reset circuitry (POR, POK, UVLO) across voltage and temperature corners to ensure proper start-up behavior.
  • Validate register maps, EEPROM configuration loads, read/write protocols, and trim test modes against design specifications.
  • Log and track verification bugs using GitLab issue tracking, applying standard workflow states (Analysis Pending, Verified) to support tapeout readiness.
  • Partner with Analog Design, Digital Design, and Systems Engineering to review coverage metrics in Jama Connect and support testcase closure.

What You Will Bring

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
  • 1–3 years of industry or relevant academic/internship experience in mixed-signal design verification or IC design.
  • Familiarity with Cadence EDA tools (Virtuoso, ADE Explorer/Assembler, AMS Designer).
  • Understanding of HDL languages (Verilog, SystemVerilog) and introductory knowledge of Verilog-A/AMS.
  • Solid grasp of fundamental analog circuits (amplifiers, bandgaps, LDOs, ADCs, oscillators) and digital logic basics.
  • Basic familiarity with Linux environments and scripting (Python, Bash, or Skill) is a plus.
  • Exposure to issue-tracking tools (e.g., GitLab) and requirements management systems (e.g., Jama Connect).
  • Curious, proactive problem-solver with strong written and verbal communication skills who enjoys learning and collaborating in a global engineering environment.

Why Allegro?

Join Allegro and become part of a team where your contributions truly matter.

We foster a culture of Real Innovation, empowering you to push boundaries, develop cutting-edge solutions, and drive continuous improvement. Your work will create a Real Impact by solving complex real-world challenges that fuel our success and shape the future of technology. You’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose. Join us—and help build what’s next.

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