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Open nowPosted yesterday

Senior Design Engineer

Altera204 open roles

Where
Regus, Madhapur
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Your applicationOpen nowSenior Design EngineerAltera · Regus, Madhapur

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The clock on this job

Early applications get read.

13.4% of postings close within 7 days. Measured by our own scanner across the market. Altera postings stay open a median of 10 days.

Share of postings closed within
  1. 2.2%1 day
  2. 4.6%3 days
  3. 13.4%7 days
  4. 21.6%14 days
  5. 36.2%30 days
  6. 59.0%60 days
This job: posted yesterday

Altera median: 10 days open

The posting

Job Details:

Job Description:

Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We are driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance.

We are seeking a talented Logic Design Engineer to develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs.

Key Responsibilities:

1. Participate in design development tasks throughout the IP development flow.

2. Develops the logic design, register transfer level (RTL) coding, and simulation for an IP.

3. Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.

4. Applies various strategies, tools, and methods to write RTL and optimize the logic to quality the design to meet the IP release requirement.

5. Involve in design example creation, simulation example creation, IP integration and release process.

6. Involve in IP design example brings up on hardware, hardware verification and failure debugging.

Qualifications:

1. 8+ years' experience with bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.

2. Experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis

3. Experience in programming with C/C++/Perl/Python/TCL/Unix Shell script

4. Experience in FPGA design and programming is a plus.

5. Experience in RTL validation is a plus.

6. Ability to work with different teams, good communication and problem-solving skills.

Job Type:

Regular

Shift:

Shift 1 (India)

Primary Location:

Regus, Madhapur

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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