The posting
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Programmable Clock India lead, Adaptive Computing Group
THE ROLE:
As the leader of the Programmable Clock Design & Methodologies team in India for AMD's Adaptive-Embedded Computing products, you will be responsible for driving the development of clocking solutions that meet the high standards of AMD's AECG products. This will involve leading a team of highly skilled engineers in India, as well as collaborating with the global Clock team of experts at the San Jose office, inventing and implementing original solutions, addressing challenging clock problems in some of the industry’s largest and most complex SOCs.
Every new Adaptive SOC brings a new set of programable Clock challenges with their latest system and functional architectures and their adoption of new semiconductor and packaging technologies. The Global Clock team works closely with functional Architecture, Programable fabric, Integration and SW teams to craft and implement new clock solutions, including new architectures, Clock IPs and development of new tools, flows & Methodology.
This can be a challenging but exciting opportunity.
THE PERSON:
This is a critical role within the company, and requires a combination of technical expertise, leadership skills, and effective communication. If you are passionate about clocking methodologies and have a track record of leading successful teams, this could be an exciting opportunity for you to join a innovative programmable Clock team at AMD.
You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging Programable Clock problems.
KEY RESPONSIBILITIES:
- Developing Programable global Clock distribution methodologies, optimizing Clock - Skew, Signal integrity and power integrity issues for AMD's next generation of programmable product families.
- Large Scale Block to Block Clock timing analysis, within the Die & Die to Die Clock interposer crossing.
- Deep analysis of timing paths to identify and debug key issues.
- Collaborate with functional IP teams (RTL, Ckt, physical design, Full Chip Timing, Integration) during the implementation and qualification of a growing number of programable Clock IPs.
- Identify key positions and required skills: Based on the team's objectives, the candidate should identify the key positions required to achieve them. These could include Circuit Design, STA, Physical Design & RTL etc.
PREFERRED EXPERIENCE:
- You should have a deep understanding of System level clocking methodologies and experience in leading teams to deliver complex projects with 15+ Years of experience. Working knowledge of Programable clocking is a plus.
- You should be an expert in the development of Programmable clocking solutions and have the ability to work effectively with global teams (USA & India) to ensure that on time product delivery with high quality is met.
- Strong Clock fundamentals (Clock switching and gating, synchronization, Clock skew balancing, Jitter, Fmax, DCD and CDC analysis).
- Familiarity with test, debug, yield, post-Silicon Validation & Characterization is a plus.
- Working experience of Package level Clock SIPI is a plus.
- Proficient in STA and methodologies for timing closure and have a good understanding of noise, cross-talk, Aging and OCV effects, among others.
- Defined timing/SDC and placement constraints for IPs.
- EDA tools, Design Compiler, ICC2, Primetime. Working knowledge of extraction and STA methodology and tools.
- Familiar with circuit modeling, including AMS sim, and worst-case corner selection.
- Familiarity with Verilog and system Verilog for design.
- Additionally, you should be a skilled communicator, able to provide technical guidance and mentorship to your team members to help them develop their skills and advance their careers.
ACADEMIC CREDENTIALS:
- BS, MS or PhD in Electrical and/or Computer Engineering, Computer Science or related field.
LOCATION:
Bangalore, India
#LI-PK2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Programmable Clock India lead, Adaptive Computing Group
THE ROLE:
As the leader of the Programmable Clock Design & Methodologies team in India for AMD's Adaptive-Embedded Computing products, you will be responsible for driving the development of clocking solutions that meet the high standards of AMD's AECG products. This will involve leading a team of highly skilled engineers in India, as well as collaborating with the global Clock team of experts at the San Jose office, inventing and implementing original solutions, addressing challenging clock problems in some of the industry’s largest and most complex SOCs.
Every new Adaptive SOC brings a new set of programable Clock challenges with their latest system and functional architectures and their adoption of new semiconductor and packaging technologies. The Global Clock team works closely with functional Architecture, Programable fabric, Integration and SW teams to craft and implement new clock solutions, including new architectures, Clock IPs and development of new tools, flows & Methodology.
This can be a challenging but exciting opportunity.
THE PERSON:
This is a critical role within the company, and requires a combination of technical expertise, leadership skills, and effective communication. If you are passionate about clocking methodologies and have a track record of leading successful teams, this could be an exciting opportunity for you to join a innovative programmable Clock team at AMD.
You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging Programable Clock problems.
KEY RESPONSIBILITIES:
- Developing Programable global Clock distribution methodologies, optimizing Clock - Skew, Signal integrity and power integrity issues for AMD's next generation of programmable product families.
- Large Scale Block to Block Clock timing analysis, within the Die & Die to Die Clock interposer crossing.
- Deep analysis of timing paths to identify and debug key issues.
- Collaborate with functional IP teams (RTL, Ckt, physical design, Full Chip Timing, Integration) during the implementation and qualification of a growing number of programable Clock IPs.
- Identify key positions and required skills: Based on the team's objectives, the candidate should identify the key positions required to achieve them. These could include Circuit Design, STA, Physical Design & RTL etc.
PREFERRED EXPERIENCE:
- You should have a deep understanding of System level clocking methodologies and experience in leading teams to deliver complex projects with 15+ Years of experience. Working knowledge of Programable clocking is a plus.
- You should be an expert in the development of Programmable clocking solutions and have the ability to work effectively with global teams (USA & India) to ensure that on time product delivery with high quality is met.
- Strong Clock fundamentals (Clock switching and gating, synchronization, Clock skew balancing, Jitter, Fmax, DCD and CDC analysis).
- Familiarity with test, debug, yield, post-Silicon Validation & Characterization is a plus.
- Working experience of Package level Clock SIPI is a plus.
- Proficient in STA and methodologies for timing closure and have a good understanding of noise, cross-talk, Aging and OCV effects, among others.
- Defined timing/SDC and placement constraints for IPs.
- EDA tools, Design Compiler, ICC2, Primetime. Working knowledge of extraction and STA methodology and tools.
- Familiar with circuit modeling, including AMS sim, and worst-case corner selection.
- Familiarity with Verilog and system Verilog for design.
- Additionally, you should be a skilled communicator, able to provide technical guidance and mentorship to your team members to help them develop their skills and advance their careers.
ACADEMIC CREDENTIALS:
- BS, MS or PhD in Electrical and/or Computer Engineering, Computer Science or related field.
LOCATION:
Bangalore, India
#LI-PK2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
