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Open nowPosted 29 days ago

芯片综合/STA工程师（存算与AI） - 芯片研发

ByteDance19,268 open roles

Where
Beijing, Chinese Mainland
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Your applicationOpen now芯片综合/STA工程师（存算与AI） - 芯片研发ByteDance · Beijing, Chinese Mainland

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The clock on this job

Early applications get read.

11.5% of postings close within 7 days. Measured by our own scanner across the market. ByteDance postings stay open a median of 9 days.

Share of postings closed within
  1. 2.0%1 day
  2. 4.3%3 days
  3. 11.5%7 days
  4. 18.1%14 days
  5. 35.6%30 days
  6. 44.6%60 days
This job: posted 29 days ago

ByteDance median: 9 days open

The posting

团队介绍：聚焦存算一体芯片设计，主要围绕AI大模型应用场景进行高能效计算技术创新，设计多款基于存算一体架构的高能效AI芯片，突破传统冯・诺依曼架构下的 "内存墙" 瓶颈，提升能效比、降低算力成本。团队具备独立流片与量产落地能力，累计申请专利近300项，核心专利覆盖“底层器件-核心架构-工程落地”全流程。同时与字节各团队算力需求整体协同，更好的发挥存算一体芯片的技术价值，共同为AI业务提供高能效算力底座。

1、负责SoC芯片中的RTL synthesis、formality、lower power check、power/STA签核、eco等工作； 2、熟悉SDC和各种timing check与timing buget，分析复杂的Timing、Clock Structure等问题； 3、与周边团队合作，完成芯片设计过程中的时钟/复位方案，低功耗方案； 4、负责复杂工艺的评估选型，LIB/MEM选型及定制化； 5、熟悉STA签核方法学，负责芯片STA签核标准制定与STA收敛等工作。

1、硕士学位及以上，微电子/电子/计算机等相关专业毕业； 2、熟悉Verilog/SDC/UPF语法和流程，熟悉TCL、Python、Perl脚本，有STA流程搭建经验者优先； 3、熟练使用genus/DC/PT/LEC/CLP等EDA工具，熟悉综合实现流程与各种优化方法； 4、熟悉DFT、总线、异步、IP、IO等设计协议，能够基于timing风险评估给出建议profile； 5、良好的团队合作精神，良好的沟通能力，英语读写顺畅。

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