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Open nowPosted 37 days ago

Principal DFT Engineer

Celero Communications, Inc.26 open roles

Pay
$200,000 – $240,000 a year
Where
Irvine, California, United States
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Your applicationOpen nowPrincipal DFT EngineerCelero Communications, Inc. · Irvine, California, United States

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The clock on this job

Early applications get read.

11.8% of postings close within 7 days. Measured by our own scanner across the market. Celero Communications, Inc. postings stay open a median of 34 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.4%3 days
  3. 11.8%7 days
  4. 18.6%14 days
  5. 35.6%30 days
  6. 45.1%60 days
This job: posted 37 days ago

Celero Communications, Inc. median: 34 days open

The posting

Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. This individual will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies that enable high quality, high volume production of complex ASIC and SoC products.

What You Will Do

  • Develop and implement DFT architecture for ASIC and SoC designs.
  • Perform scan insertion, scan chain planning, and scan compression implementation.
  • Generate and validate ATPG patterns and analyze fault coverage results.
  • Implement and verify MBIST, and other on-chip test features.
  • Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
  • Support JTAG and boundary-scan implementation and debug.
  • Drive DFT signoff activities and manufacturing test readiness.
  • Participate in silicon bring-up, failure analysis, and yield improvement efforts.

What You Will Bring

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
  • 8+ years of ASIC/SoC DFT experience.
  • Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
  • Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
  • Knowledge of Verilog/SystemVerilog and digital design fundamentals.
  • Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
  • Results-driven engineer with strong debugging abilities.
  • Comfortable working in fast-paced cross-functional environments.
  • Passion for delivering high-quality silicon products.

Preferred Qualifications

  • Experience with advanced-node semiconductor technologies.
  • Hands-on experience with MBIST, compression architectures, and JTAG.
  • Knowledge of timing closure, physical design impacts, and low-power design techniques.
  • Experience supporting silicon validation and manufacturing production ramps.
  • Strong communication and cross-functional collaboration skills. Annual Base Salary Range for US: $200,000 - $240,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
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