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Open nowPosted 199 days ago

Principal PLL Design Engineer

Celero Communications, Inc.26 open roles

Pay
$150,000 – $250,000 a year
Where
Irvine, CA or San Jose, CA
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Your applicationOpen nowPrincipal PLL Design EngineerCelero Communications, Inc. · Irvine, CA or San Jose, CA

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The clock on this job

Early applications get read.

11.5% of postings close within 7 days. Measured by our own scanner across the market. Celero Communications, Inc. postings stay open a median of 34 days.

Share of postings closed within
  1. 2.0%1 day
  2. 4.3%3 days
  3. 11.5%7 days
  4. 18.1%14 days
  5. 35.6%30 days
  6. 44.6%60 days
This job: posted 199 days ago

Celero Communications, Inc. median: 34 days open

The posting

Are you a PLL Design Engineer passionate about developing the high-speed clocking technology that will power the next generation of AI infrastructure? Join our fast-growing semiconductor startup and help deliver disruptive High-Speed Interconnect solutions for tomorrow's optical networks.

We are seeking a High-Speed CMOS PLL Analog Design Engineer to play a key role in the architecture and design of advanced clocking circuits for next-generation optical transceivers, high-speed SerDes, and high-performance ADC/DAC systems. In this role, you will architect and design state-of-the-art PLLs for industry-leading transceivers, working alongside a world-class team to solve some of the most challenging mixed-signal design problems in advanced CMOS technologies. This is an opportunity to make a significant technical impact while helping build groundbreaking products from the ground up.

Locations: Irvine, CA (HQ) | San Jose, CA | Vancouver, BC | Ottawa, ON

What You Will Do: • Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range • Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre • Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization • Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies • Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment • Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies

What You Will Bring: • Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience • Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes) • Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs • Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling • Strong communication and documentation skills

Annual Base Salary Range for US: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

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