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Open nowPosted 123 days ago

Staff Physical Design Engineer

Credo40 open roles

Where
Singapore Office, Singapore
Work mode
On site
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Your applicationOpen nowStaff Physical Design EngineerCredo · Singapore Office, Singapore

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The clock on this job

Early applications get read.

11.8% of postings close within 7 days. Measured by our own scanner across the market. Credo postings stay open a median of 1 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.4%3 days
  3. 11.8%7 days
  4. 18.6%14 days
  5. 35.6%30 days
  6. 45.1%60 days
This job: posted 123 days ago

Credo median: 1 days open

The posting

Job description

Credo is seeking a Staff Physical Design Engineer to join our Digital R&D team. In this role, you will lead all aspects of physical design and implementation for SoC designs, collaborating closely with frontend and PD/Integration teams across our China and Taiwan offices to drive successful tape outs.

Why Credo

  • Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
  • People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
  • Possibilities: Our belief shapes what’s next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.

Qualifications

Basic Qualifications

  • BS/MS in EE/CS with a minimum of 8+ years of recent hands-on experience as a Physical Design Engineer.
  • Familiar with hierarchical physical design strategies, methodologies.
  • Experience with 5nm and lower technology nodes.
  • Proven track records of handling chip level P&R independently and taping out complex SOC chips under tight schedule pressure.
  • Strong proficiency with EDA tools such as Cadence, Innovus, and Synopsys Fusion Compiler.
  • Solid knowledge on static timing analysis (PrimeTime/Tempus), EM/IR-Drop/crosstalk analysis (PTSI/Voltus/Redhawk), extraction (Quantus/StarRC).
  • Familiar with DRC, Antenna, LVS, ERC tools like Calibre.

Responsibilities

  • Lead and drive Top-Level/IP/block-level physical implementation from RTL to GDSII, focusing on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems.
  • Participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, power planning/analysis, place-and-route, physical verification and sign-off.
  • Perform static timing analysis, power and noise analysis and physical verification.
  • Deliver IP hardening/integration and verification.
  • Work closely with frontend and integration team to ensure successful tape outs.

Job benefits

Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI. ​ Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world. ​ Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [email protected].

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