Skip to content
CV Rocket
Get started
How it worksThe enginePricingBlogContactSign in

Open nowPosted today

Senior Analog and Mixed Signal Design Engineer

Intel692 open roles

Where
US Oregon Hillsboro
Get the CV for this job

From $25 per CV, paid once. No subscription.

Your applicationOpen nowSenior Analog and Mixed Signal Design EngineerIntel · US Oregon Hillsboro

  1. YouYes, apply to this one.

  2. CV RocketCV written for this posting.

  3. 25 readersRecruiter, hiring manager, skeptic. Round after round.

  4. CV RocketApplied on Intel's own form.

The reply lands in your private mailbox

3×more interviews than doing it yourself with ChatGPT.

The clock on this job

Early applications get read.

12.3% of postings close within 7 days. Measured by our own scanner across the market. Intel postings stay open a median of 24 days.

Share of postings closed within
  1. 2.1%1 day
  2. 4.5%3 days
  3. 12.3%7 days
  4. 19.7%14 days
  5. 35.6%30 days
  6. 58.0%60 days
This job: posted today

Intel median: 24 days open

The posting

Job Details:

Job Description:

The Group

Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) drives pathfinding and development of the analog/mixed-signal and high-speed I/O IP that defines what Intel's leading-edge process technologies can deliver. The High-Speed I/O team develops SerDes and die-to-die interface reference designs and test chips that co-optimize Intel process technology with next-generation wireline standards, including high-speed PAM4 electrical links, PCIe, UCIe, and HBM.

The Role

We are seeking a senior technical expert in high-speed SerDes circuit design and SerDes system architecture. You will own SerDes link architecture on Intel's leading technology test chips, from link budget and equalization strategy down to transistor-level design of the critical analog front-end and clocking blocks. You will also translate link requirements into device, interconnect, and design-rule requirements that shape future Intel process nodes. This is a senior individual-contributor role with technical leadership across design, layout, and measurement engineers.

Responsibilities

  • Define SerDes link architecture for next-generation interfaces (224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, UCIe): channel analysis, link budget, jitter and noise budgeting, and equalization partitioning across TX FFE, RX CTLE, DFE, and ADC/DSP-based receivers.
  • Build and maintain system-level link models (statistical and time-domain, in MATLAB or Python; COM and IBIS-AMI based) and use them to derive block-level specifications for TX, RX, ADC, and clocking circuits.
  • Lead transistor-level design of critical SerDes blocks: TX drivers (SST/CML) with FFE, RX AFE (CTLE, VGA, termination, T-coil and ESD co-design), DFE and slicers, time-interleaved ADC front ends, CDR and phase interpolators, LC and ring PLLs, and clock distribution.
  • Drive test-chip definition, integration, tapeout readiness, and silicon bring-up; correlate measured BER, eye, jitter, and power against models, and lead root-cause analysis of silicon-to-model gaps.
  • Translate SerDes requirements into process and PDK requirements (device fT/fmax and parasitics, BEOL RC, inductor Q, matching, ESD capacitance budget, reliability and aging) and drive design-technology co-optimization with process, PDK, and template-library teams.
  • Provide technical leadership: mentor engineers, lead design reviews, and represent Intel Foundry in technical engagements with IP partners and foundry customers.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

  • Bachelors Degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 6+ years of industry experience in high-speed wireline SerDes circuit design experience -OR- Master's degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 4+ years of industry experience in high-speed wireline SerDes circuit design, -OR- Ph.D. in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 2+ years of industry experience in high-speed wireline SerDes circuit design.
  • Experience in Transistor-level design of SerDes TX, RX, or clocking circuits in at least one silicon-proven design at 28 Gb/s per lane or higher.
  • Experience in at least one of the following:SerDes link architecture: channel and link-budget analysis or equalization trade-off studies used to set block-level specifications. Lab validation of high-speed links: BER, eye, or jitter measurement and correlation to simulation. Behavioral or statistical link modeling in MATLAB or Python.

Preferred Qualifications

  • Experience with Silicon-proven designs at 56 Gb/s PAM4 or higher, in FinFET or GAA CMOS; multiple tape-outs with block ownership.
  • Experience across all three areas above (architecture, lab validation, and link modeling).
  • Experience in ADC/DSP-based receivers at 112 Gb/s PAM4 or higher, including time-interleaved ADC design. - 224 Gb/s-class link development (IEEE 802.3dj, OIF CEI-224G). - PCIe Gen6/Gen7 PHY or UCIe die-to-die PHY development.
  • Design experience on 5nm-class or more advanced nodes, with design-technology co-optimization experience with process teams.
  • Experience in package and channel co-design: package/PCB channel modeling, signal and power integrity, crosstalk.
  • Experience with first-author publications at ISSCC, VLSI Symposium, CICC, or JSSC; patents in SerDes circuits or architecture.
  • Technical leadership of a multi-engineer SerDes design team through a full PHY delivery.

Take the next step to make an impact at Intel. Join us in redefining possibilities, driving innovation, and shaping the future of technology.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, California, Santa Clara

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

From $25, paid onceGet the CV for this job

What happens when you press

One press. We do the rest.

  1. A CV for this posting

    Written against Intel's own wording, from every piece of relevant proof in your profile.

  2. 25 readers review it

    Recruiter, hiring manager, skeptic and more read every draft, round after round. You get the best round.

    The review screen in CV Rocket: how each CV was read, round by round.

  3. We apply on Intel's form

    Our application engine gets through the hardest forms there are. Where a question needs you, AI suggests the best answer. Don't want us applying from our IP addresses? Use our Chrome extension: we apply straight from your own browser.

    An application in CV Rocket: every answer filled in on the employer's form.

  4. Every reply, sorted

    Intel's answer lands in your private mailbox, and we classify it on arrival: interview, question, rejection.

    The CV Rocket inbox: each employer reply classified as an interview, an action or a rejection.

  5. Reply with AI

    AI helps you write the email, checks it and sends it. We show you whether the recruiter read it.

  6. The interview in your calendar

    Full integration with your calendar. The invitation goes straight in.

    An interview invitation in the CV Rocket inbox, added to the candidate's calendar.
Get the CV for this job

From $25 per CV, paid once. No subscription.

Why it works

3×

more interviews than doing it yourself with ChatGPT.

ChatGPT writes a CV and never learns what happened to it. We see every reply. For each CV we know:

  • How it was written, and how the review scored it
  • When we applied, and how long after the posting went up
  • Which posting, which company, which city
  • Who got the interview, and who heard nothing

That is how we know which CVs get called.

Get the CV for this job

From $25 per CV, paid once. No subscription.

The numbers game

More applications. More interviews.

Every application goes out with its own CV, written for that posting and paid once. Send enough of them and the law of large numbers finds you the job.

Get the CV for this job
By hand5–10
With CV Rocket100
applications a day

Nearby

Live postings like this one

Same employer first, then the same role elsewhere.

Before you press

Straight answers

Get the CV for this job

From $25 per CV, paid once. No subscription.

What if my background isn't good enough?

We make the most of the background you have. The CV uses every piece of relevant proof your profile holds, and one of the 25 readers reads your whole profile and flags what the CV left out.

Do you really apply for me?

Yes, on the employer's own form, the hardest ones included. Where a question needs you, you answer it right there and AI suggests the best answer. Don't want us applying from our IP addresses? Use our Chrome extension: we apply straight from your own browser.

Is it a subscription?

No. You pay once per CV, from $25. Every application goes out with its own CV, written for that posting.

One job. One CV.
Paid once.

Pick the posting you want. We write for it, apply for you and catch the reply.

Get the CV for this job

From $25 per CV, paid once. No subscription.