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Open nowPosted 47 days ago

Analog Layout Engineer (Lead)

Kandou AI42 open roles

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Your applicationOpen nowAnalog Layout Engineer (Lead)Kandou AI · Reading

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  6. 52.7%60 days
This job: posted 47 days ago

The posting

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

Job title: Analog Layout Engineer (Lead)

Location: EU/CH/UK

Responsibility

- Position in custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip to chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodes

- Layout and verification of very high-speed analog circuits

- Interact closely with the design team to understand requirements and implement solutions

- Support IP and chip level integration

- Support and interact with customers on requirements, and IP delivery

- Exposure to flip-chip package technologies

Experience

- Must have experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits

- Must have expertise in layout of high-speed/frequency circuits like amplifiers, oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, buffers, regulators, filters, data converters, etc.

- Understanding of layout approaches and techniques for high-speed circuits, matching constraints, minimization of parasitics, power grids and ESD requirements

- Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm

- User of EDA tool for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc.

Skills

- Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player

- Manage workload and schedules and report to internal management team

- Background in Semiconductor Physics

Education

- Graduate in E.E.

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