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Open nowPosted 64 days ago

DFT Engineer CH, UK

Kandou AI42 open roles

Where
Saint-Sulpice
Work mode
Hybrid
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Your applicationOpen nowDFT Engineer CH, UKKandou AI · Saint-Sulpice

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11.5% of postings close within 7 days. Measured by our own scanner across the market.

Share of postings closed within
  1. 2.1%1 day
  2. 4.4%3 days
  3. 11.5%7 days
  4. 18.1%14 days
  5. 35.6%30 days
  6. 44.6%60 days
This job: posted 64 days ago

The posting

Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

We are actively seeking a resourceful DFT Engineer based in Lausanne, Switzerland or UK

Key Responsibilities:

- Hierarchical MBIST and scan insertion, BSD implementation

- ATPG pattern generation, coverage analysis, converging to high coverage metrics

- Pattern simulations with timing

- Defining test mode timing constraints, analyzing the timing reports and converge timing

- Developing cycle accurate functional patterns using IJTAG methodology

- Closely working with the test and production engineering teams to debug and bring up devices at probe and final test

- Debugging silicon issues

Skills:

- Excellent communication skills, and strong team player with can do type of attitude

- Excellent debugging skills

- Good scripting skills to develop automation

Qualifications:

- 5+ years of DFT experience including implementation, test pattern development, and simulation

- Proven experience in contributing to DFT solution to complex designs

- Experience working with IJTAG methodologies

- Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies

- Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics

- Good debug capabilities in simulating patterns with timing

- Experience with industry standard EDA tools for DFT, timing, and simulation

- Knowledge of System Verilog

Education:

- Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher)

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