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Freelance Digital Design Engineer

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This job: first seen 2 hours ago

The posting

Freelance Talent Pool · Future Assignments

No immediate requirement. This posting is intended to build our freelance talent pool and contact database for future assignments. No assignment or start date is currently confirmed.

Digital RTL design for ASIC / SoC / IP

We are building our network of independent RTL design experts to develop digital blocks and integrate them into future ASIC / SoC architectures.

Share Your Freelance ProfileView Technical Scope

Start date

Future need, no date confirmed

Engagement

Freelance assignment

Location and work mode

Moirans / Grenoble, on-site or remote depending on the project

What We Value

  • Autonomy, design rigor, a focus on quality and delivery against project milestones.
  • Ability to identify technical risks and propose practical solutions.
  • Clear communication with multidisciplinary teams and high-quality documentation.
  • Professional technical English for project discussions and documentation.

Before sharing your profile

Please do not share confidential design details. High-level project examples are sufficient.

The activities and deliverables below illustrate possible scopes for future collaborations. They will be tailored to each project.

Potential Responsibilities

  • Analyze functional specifications and translate requirements into digital microarchitecture, interfaces and RTL blocks.
  • Design, develop and maintain synthesizable modules in VHDL and/or Verilog / SystemVerilog.
  • Integrate IP blocks, peripherals and interfaces into ASIC / SoC architectures at block or top level.
  • Perform basic RTL checks, including simulation, lint and CDC / RDC analysis as applicable, and resolve identified issues.
  • Contribute to logic synthesis, timing constraint analysis and PPA (power, performance and area) optimization.
  • Collaborate with verification, DFT and physical implementation teams to deliver a reliable, well-documented RTL handoff.

Technical Expertise

  • Proven experience in RTL design for complex ASICs, SoCs or IP blocks.
  • Proficiency in VHDL and/or Verilog / SystemVerilog, synthesizable coding methodologies and RTL simulation.
  • Sound understanding of synchronous architectures, FSMs, pipelines, clock/reset design, buses and communication interfaces.
  • Hands-on experience with simulation and lint tools such as Questa, VCS, Xcelium or equivalent solutions.
  • Knowledge of logic synthesis, SDC constraints and timing / CDC issues.
  • Use of Git and Tcl, Python or shell scripts in a Linux environment.

Typical Deliverables

Detailed architecture and documentation for the implemented blocks and interfaces.

Structured, synthesizable, version-controlled RTL code with supporting scripts.

Simulation, lint, CDC and synthesis results, with tracking of anomalies and known limitations.

Constraints, reports and handoff materials for verification and physical implementation teams.

Support for design reviews, integration and resolution of open issues.

Nice to Have

  • Experience with AMBA AXI / AHB / APB, SPI, I²C, UART, Ethernet or other digital interfaces.
  • Knowledge of ARM / RISC-V architectures, microcontrollers, accelerators or embedded subsystems.
  • Experience with formal verification, SVA assertions and UVM environments.
  • Experience with low-power strategies such as clock gating and power domains / UPF, and design for test (DFT).
  • Experience with FPGA prototyping and analog / mixed-signal block integration.

Collaboration Arrangements

No immediate requirement. This posting is intended to build our freelance talent pool and contact database for future assignments. No assignment or start date is currently confirmed.

When a future need is identified, the technical scope, schedule, duration, location, remote working arrangements and commercial terms will be discussed based on the project and the freelancer’s expertise.

About XDigit

XDigit is a French design house specializing in custom integrated circuits and embedded electronic systems. We serve markets including IoT, medical, space, automotive and smart cities, with expertise in analog, digital and mixed-signal design. We support ASIC and silicon IP projects from specifications through to GDSII.

We also develop MASSAR, a patented analog-to-digital converter for high-performance image sensors, marketed as silicon IP.

Join Our Freelance Talent Pool

Share your CV or professional profile, availability, location and a few non-confidential examples of digital RTL design projects. We will contact you if a future requirement matches your expertise.

Share Your Freelance Profile

Contact: [email protected] · www.xdigit.fr

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