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Freelance Physical Implementation Design Engineer

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This job: first seen 2 hours ago

The posting

Freelance Talent Pool · Future Assignments

No immediate requirement. This posting is intended to build our freelance talent pool and contact database for future assignments. No assignment or start date is currently confirmed.

Digital physical implementation for ASIC / SoC

We are building our network of independent physical implementation experts for future ASIC / SoC projects, working with digital design, verification and integration teams.

Share Your Freelance ProfileView Technical Scope

Start date

Future need, no date confirmed

Engagement

Freelance assignment

Location and work mode

Location and remote work to be defined for each project

What We Value

  • A focus on silicon quality, problem solving and delivery against milestones.
  • Technical autonomy, thorough documentation and clear communication of risks.
  • Effective collaboration with multidisciplinary teams and active participation in design reviews.
  • Professional technical English for documentation and project discussions.

Before sharing your profile

Please do not share confidential design details. High-level project examples are sufficient.

The activities and deliverables below illustrate possible scopes for future collaborations. They will be tailored to each project.

Potential Responsibilities

  • Take ownership of all or part of the RTL-to-GDSII physical design flow: synthesis / netlist handoff, floorplanning, placement, clock tree synthesis (CTS) and routing.
  • Define and optimize the floorplan, physical constraints and power distribution network (power planning / PDN).
  • Drive timing closure and PPA (performance, power and area) optimization in collaboration with RTL and STA teams.
  • Run physical quality checks and contribute to DRC / LVS / antenna / density closure within the agreed scope.
  • Analyze congestion, hold/setup timing, signal integrity, IR drop and electromigration issues, and propose corrective actions.
  • Prepare the deliverables and technical reviews required for sign-off and GDSII delivery.

Technical Expertise

  • Proven experience in digital ASIC / SoC physical implementation at block and/or top level.
  • Proficiency with at least one industrial place-and-route suite: Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler.
  • Hands-on experience with static timing analysis (STA), SDC constraints and multi-corner / multi-mode (MCMM) timing closure.
  • Sound understanding of physical verification and sign-off flows, and delivery formats including LEF/DEF, Liberty and GDSII.
  • Ability to automate tasks using Tcl and, ideally, Python / shell in a Linux environment.

Typical Deliverables

Floorplan and placement / routing strategy validated with the project team.

Implementation database, reproducible scripts and updated constraint files.

Timing, PPA, congestion and physical quality reports, with tracking of open issues.

Handoff / sign-off package, GDSII files and traceability documentation, depending on the assignment scope.

Nice to Have

  • Experience with advanced CMOS nodes, complex SoCs or low-power architectures.
  • Familiarity with sign-off tools such as PrimeTime / Tempus, Calibre / Pegasus or Voltus / RedHawk, depending on the project.
  • Experience integrating macros, SRAMs, third-party IP and block interfaces within a top-level hierarchy.
  • Awareness of manufacturing constraints, silicon robustness and foundry interactions.

Collaboration Arrangements

No immediate requirement. This posting is intended to build our freelance talent pool and contact database for future assignments. No assignment or start date is currently confirmed.

When a future need is identified, the technical scope, schedule, duration, location, remote working arrangements and commercial terms will be discussed based on the project and the freelancer’s expertise.

About XDigit

XDigit is a French design house specializing in custom integrated circuits and embedded electronic systems. We serve markets including IoT, medical, space, automotive and smart cities, with expertise in analog, digital and mixed-signal design. We support ASIC and silicon IP projects from specifications through to GDSII.

We also develop MASSAR, a patented analog-to-digital converter for high-performance image sensors, marketed as silicon IP.

Join Our Freelance Talent Pool

Share your CV or professional profile, availability, location and a few non-confidential examples of physical implementation projects. We will contact you if a future requirement matches your expertise.

Share Your Freelance Profile

Contact: [email protected] · www.xdigit.fr

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